CAJ | 학술논문

弹性缓冲器是PCIE,USB等高速串行总线物理层接收器的重要组成部分,用于物理层接收器中恢复时钟与本地时钟的频率补偿和相位同步,对信号的传输质量起着重要作用。基于PCIE2．0协议,采用存储器常半满的实现方式,设计一款深度、宽度均为10的弹性缓冲器。该弹性缓冲器应用于PCIE2．0的物理层设计中,并采用SMIC 55 nm CMOS 工艺实现。芯片测试结果表明,该弹性缓冲器满足 PCIE2．0协议的要求,可正常工作于500 MHz的时钟频率下,实现恢复时钟与本地时钟的频率和相位补偿,保证了接收器正常接收数据。
탄성완충기시PCIE,USB등고속천행총선물리층접수기적중요조성부분,용우물리층접수기중회복시종여본지시종적빈솔보상화상위동보,대신호적전수질량기착중요작용。기우PCIE2．0협의,채용존저기상반만적실현방식,설계일관심도、관도균위10적탄성완충기。해탄성완충기응용우PCIE2．0적물리층설계중,병채용SMIC 55 nm CMOS 공예실현。심편측시결과표명,해탄성완충기만족 PCIE2．0협의적요구,가정상공작우500 MHz적시종빈솔하,실현회복시종여본지시종적빈솔화상위보상,보증료접수기정상접수수거。
Elastic buffer is a very important function in receiver at high-speed serial protocols such as PCI Express ( PCIE) and USB. The frequency delta and phase delta are managed perfectly to ensure data integrity by the elastic buffer when bridging local clock domain and recovered clock domain. This paper proposes elastic buffer logic in primed method to satisfy PCIE2. 0 protocol specification. The width and depth of the elastic buffer are both 10. The proposed logic is integrated into Physical Layer ( PHY ) and implemented based on 55 nm CMOS process of SMIC. The result to be measured well agreeds with the actual requirement. It can work well under the frequency of 500 MHz and ensure data to receive data correctly.