基于FPGA和符号LMS算法的自适应滤波器设计
기우FPGA화부호LMS산법적자괄응려파기설계
Design of Adaptive Filter Based on FPGA and Signum-LMS Algorithm
  • 万方数据
    电子器件 전자기건
    JOURNAL OF ELECTRON DEVICES
    2014年 5期 904-907 ,共4页

    邱陈辉%李锋%徐祖强

    구진휘%리봉%서조강

    数字信号处理%自适应滤波器%最小均方%符号最小均方%现场可编程门阵列%流水线 數字信號處理%自適應濾波器%最小均方%符號最小均方%現場可編程門陣列%流水線
    수자신호처리%자괄응려파기%최소균방%부호최소균방%현장가편정문진렬%류수선
    digital signal processing%adaptive filter%least mean square(LMS)%signum-least mean square(SLMS)%field programmable gate array(FPGA)%pipelining
    为了减少实现基于FPGA和LMS算法的自适应滤波器过多消耗硬件资源的问题，提出了符号LMS算法，通过降低乘法运算的次数来提高自适应滤波器的运行速度，并使用流水线技术进行优化。软件仿真验证了符号LMS算法的可行性，硬件仿真证实了采用该算法和流水线技术的自适应滤波器的优越性。
    위료감소실현기우FPGA화LMS산법적자괄응려파기과다소모경건자원적문제，제출료부호LMS산법，통과강저승법운산적차수래제고자괄응려파기적운행속도，병사용류수선기술진행우화。연건방진험증료부호LMS산법적가행성，경건방진증실료채용해산법화류수선기술적자괄응려파기적우월성。
    To decrease the consumption of hardware resource of adaptive filter based on FPGA and LMS algorithm, signum-LMS algorithm is proposed. The processing speed of adaptive filter is increased by reducing the number of multiplications and optimized by pipelining technology. Software simulation verifies the feasibility of signum-LMS al-gorithm. Hardware simulation proves the superiorities of the adaptive filter using the proposed algorithm and pipelining technology.
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