电子器件
電子器件
전자기건
JOURNAL OF ELECTRON DEVICES
2014年
5期
812-815
,共4页
戴强%薛颜%杨霄垒%周启才%吴俊%郭良权
戴彊%薛顏%楊霄壘%週啟纔%吳俊%郭良權
대강%설안%양소루%주계재%오준%곽량권
流水线模数转换器%伪随机序列%失调误差%电容失配误差
流水線模數轉換器%偽隨機序列%失調誤差%電容失配誤差
류수선모수전환기%위수궤서렬%실조오차%전용실배오차
pipelined analog-to-digital converter%pseudo-random sequence%offset voltage%mismatches of capacitor
设计一种用于高速高精度流水线ADC的流水线ADC子级电路,采用伪随机序列控制子ADC电路中比较器阵列的参考比较电压。比较器的高低位被随机分配,消除某个比较器的固有失调对子ADC量化的影响,温度计码的伪随机性可以消除MDAC电容的失配误差对余量输出的影响。电路采用0.18μm 1P5M 1.8 V CMOS工艺,运用于12 bit 250 Msample/s流水线ADC电路中,实际测得流水线ADC电路的SNR为69.92 dB,SFDR为81.17 dB。
設計一種用于高速高精度流水線ADC的流水線ADC子級電路,採用偽隨機序列控製子ADC電路中比較器陣列的參攷比較電壓。比較器的高低位被隨機分配,消除某箇比較器的固有失調對子ADC量化的影響,溫度計碼的偽隨機性可以消除MDAC電容的失配誤差對餘量輸齣的影響。電路採用0.18μm 1P5M 1.8 V CMOS工藝,運用于12 bit 250 Msample/s流水線ADC電路中,實際測得流水線ADC電路的SNR為69.92 dB,SFDR為81.17 dB。
설계일충용우고속고정도류수선ADC적류수선ADC자급전로,채용위수궤서렬공제자ADC전로중비교기진렬적삼고비교전압。비교기적고저위피수궤분배,소제모개비교기적고유실조대자ADC양화적영향,온도계마적위수궤성가이소제MDAC전용적실배오차대여량수출적영향。전로채용0.18μm 1P5M 1.8 V CMOS공예,운용우12 bit 250 Msample/s류수선ADC전로중,실제측득류수선ADC전로적SNR위69.92 dB,SFDR위81.17 dB。
A sub-circuit for high-speed, high-resolution pipelined ADC is presented. Reference voltages in comparators array are controlled by pseudorandom sequences. MSBs and LSBs of comparators are assigned randomly,accordingly the effect of offset of some comparator on ADC quantization is eliminated. Pseudo-random thermometer code cancels the effect of the mismatches of MDAC capacitors on residue output. This circuit implemented in 0. 18 μm 1P5M 1. 8 V CMOS process is applied to a 12-bit 250 Msample/s pipelined ADC. Test results shows that the ADC has an SNR of 69 . 92 dB and an SFDR of 81 . 17 dB.