CAJ | 학술논문

大规模集成电路通常隐含难以检测的设计错误，而在使用过程中又可能产生新的故障点。对故障效应的传播路径和范围进行准确评估，有助于确定关键模块是否受到故障的影响和定位抑制故障效应传播的关键点。然而，常规的故障效应传播分析方法往往忽略了逻辑门对故障传播的阻断效应，以及扇出重回聚区域对故障效应传播的影响。提出了一种精确的故障效应传播模型，并采用布尔逻辑函数对所提出的模型进行了形式化描述。实验结果表明：所提出的模型可对故障效应的传播范围进行更为准确地评估，并显著降低误报率。
대규모집성전로통상은함난이검측적설계착오，이재사용과정중우가능산생신적고장점。대고장효응적전파로경화범위진행준학평고，유조우학정관건모괴시부수도고장적영향화정위억제고장효응전파적관건점。연이，상규적고장효응전파분석방법왕왕홀략료라집문대고장전파적조단효응，이급선출중회취구역대고장효응전파적영향。제출료일충정학적고장효응전파모형，병채용포이라집함수대소제출적모형진행료형식화묘술。실험결과표명：소제출적모형가대고장효응적전파범위진행경위준학지평고，병현저강저오보솔。
Large scale integrated circuits tend to include hard-to-detect design faults. In addition, new faults may be produced during runtime. Precise estimate of both the path and region where fault effects propagate to can help determine if critical components will be affected by the fault and can locate key nodes for fault propagation suppres-sion. However, typical fault effect propagation analysis methods usually ignore the fact that fault effect propagation can be blocked by Boolean gates under certain input combinations and affected by reconvergent fanout regions. In this paper, we propose a precise model for fault effect propagation and present a formal description of such model u- sing Boolean functions. Experimental results and their analysis show preliminarily that the proposed model achieves more precise estimation of the region that will be influenced by fault effects while significantly reducing false posi-tives.