CAJ | 학술논문

RapidIO总线是第三代总线的代表，是处理器之间实现互联的最佳选择。但国内对于此技术的研究尚处于起步阶段，使用者也多以购买国外成熟IP为主。文中基于RapidIO V1.3协议，介绍了一种RapidIO总线的设计和实现方法，之后对其进行了全面的虚拟平台测试和FPGA平台测试。测试结果表明，该RapidIO总线符合RapidIO V1.3协议，且设计实现方式简单，复用性好，可以作为RapidIO接口方便地应用于FPGA和芯片设计中。
RapidIO총선시제삼대총선적대표，시처리기지간실현호련적최가선택。단국내대우차기술적연구상처우기보계단，사용자야다이구매국외성숙IP위주。문중기우RapidIO V1.3협의，개소료일충RapidIO총선적설계화실현방법，지후대기진행료전면적허의평태측시화FPGA평태측시。측시결과표명，해RapidIO총선부합RapidIO V1.3협의，차설계실현방식간단，복용성호，가이작위RapidIO접구방편지응용우FPGA화심편설계중。
The RapidIO bus as one of the representatives of the third generation bus,is the best choice of the interconnection between pro-cessors. But in the domestic,the study of RapidIO bus is just begun,and the RapidIO IP is bought from outland mostly. Based on the Ra-pidIO V1. 3 protocol,describe a design and implementation method for the RapidIO bus,and has carried on the comprehensive test in vir-tual platform and FPGA platform. The simulation result shows that,this design meets the RapidIO V1. 3 protocol,and is simple to imple-ment,has good reusability,and can be easily used in the design of FPGA and chip as RapidIO interface.