太赫兹科学与电子信息学报
太赫玆科學與電子信息學報
태혁자과학여전자신식학보
Information and Electronic Engineering
2014年
5期
757-760
,共4页
高冲击%预采集%高速采集%QuartusⅡ9.0软件
高遲擊%預採集%高速採集%QuartusⅡ9.0軟件
고충격%예채집%고속채집%QuartusⅡ9.0연건
high shock%acquisition in advance%high velocity data acquisition%QuartusⅡ9.0
介绍了数据采集存储系统硬件组成与技术指标、高冲击条件下电路设计方法及元器件选择原则、并行高速多通道数据采集与数据存储、数据预采集技术、系统动态参数设置等关键技术，利用甚高速集成电路硬件描述语言(VHDL)和 QuartusⅡ9.0软件完成了系统原理设计和软件仿真，并设计了系统原理样机。仿真实验证明设计的系统实现了16通道100 kHz~500 kHz 的数据采集和存储，能完成失重触发和指定通道阈值触发，系统运行稳定可靠。
介紹瞭數據採集存儲繫統硬件組成與技術指標、高遲擊條件下電路設計方法及元器件選擇原則、併行高速多通道數據採集與數據存儲、數據預採集技術、繫統動態參數設置等關鍵技術，利用甚高速集成電路硬件描述語言(VHDL)和 QuartusⅡ9.0軟件完成瞭繫統原理設計和軟件倣真，併設計瞭繫統原理樣機。倣真實驗證明設計的繫統實現瞭16通道100 kHz~500 kHz 的數據採集和存儲，能完成失重觸髮和指定通道閾值觸髮，繫統運行穩定可靠。
개소료수거채집존저계통경건조성여기술지표、고충격조건하전로설계방법급원기건선택원칙、병행고속다통도수거채집여수거존저、수거예채집기술、계통동태삼수설치등관건기술，이용심고속집성전로경건묘술어언(VHDL)화 QuartusⅡ9.0연건완성료계통원리설계화연건방진，병설계료계통원리양궤。방진실험증명설계적계통실현료16통도100 kHz~500 kHz 적수거채집화존저，능완성실중촉발화지정통도역치촉발，계통운행은정가고。
The hardware architecture of data acquisition and storage, the method of circuit design and the principle of components option under high shock environment, parallel multi-channel high velocity data acquisition and data storage,data acquisition in advance, and dynamic setting of parameters are introduced in this paper. The system is modularly designed by using Very-high-speed integrated circuit Hardware Description Language(VHDL) and QuartusⅡ9.0 software, and the prototype is designed as well. The simulation results indicate that the proposed system can realize 16 channels data acquisition and storage with 100kHz-500kHz sampling frequencies, and it is controlled by the traixial acceleration sensor and the threshold trigger based appointed channel. Its stability and reliability are verified.
