电测与仪表
電測與儀錶
전측여의표
ELECTRICAL MEASUREMENT & INSTRUMENTATION
2014年
20期
105-108
,共4页
电力线信道%LDPC码%FPGA%并行译码结构%BP算法
電力線信道%LDPC碼%FPGA%併行譯碼結構%BP算法
전력선신도%LDPC마%FPGA%병행역마결구%BP산법
power line channel%LDPC%FPGA%parallel decode structure%BP algorithm
电力线信道的噪声干扰很强，严重影响通信系统性能。文章提出了一种适于电力线通信中LDPC码的译码器硬件结构优化方法，并通过FPGA设计实现。算法的修正过程只包含简单的算术和逻辑运算，便于FPGA实现。本文方案提供的结构与常用的部分并行译码结构相比，节省了大量硬件资源。经软硬件仿真验证，硬件BP实现结构性能接近浮点BP算法，能应用于电力线通信等信噪比较低的传输领域。
電力線信道的譟聲榦擾很彊，嚴重影響通信繫統性能。文章提齣瞭一種適于電力線通信中LDPC碼的譯碼器硬件結構優化方法，併通過FPGA設計實現。算法的脩正過程隻包含簡單的算術和邏輯運算，便于FPGA實現。本文方案提供的結構與常用的部分併行譯碼結構相比，節省瞭大量硬件資源。經軟硬件倣真驗證，硬件BP實現結構性能接近浮點BP算法，能應用于電力線通信等信譟比較低的傳輸領域。
전력선신도적조성간우흔강，엄중영향통신계통성능。문장제출료일충괄우전력선통신중LDPC마적역마기경건결구우화방법，병통과FPGA설계실현。산법적수정과정지포함간단적산술화라집운산，편우FPGA실현。본문방안제공적결구여상용적부분병행역마결구상비，절성료대량경건자원。경연경건방진험증，경건BP실현결구성능접근부점BP산법，능응용우전력선통신등신조비교저적전수영역。
In a broadband low voltage power line channel,the interference from channel noise is heavy and results in a poor communication performance. This paper presents a optimization methods of the decoder of LDPC code for power line communication system,and implementation through FPGA. The correction process of this algorithm just includes simple arithmetic and logic operations,which is easy to be implemented by FPGA. Experiment has proved,compared with usual partial parallel decode structure,structure provided by this paper saves much hardware resources. Software and hardware simulations show that the proposed scheme approaches to the performance of a floating-point calcula-tion based the BP algorithm. Therefore,it can be widely used in power line communications and so on with low signal-to-noise ratio transmission.
