电子设计工程
電子設計工程
전자설계공정
ELECTRONIC DESIGN ENGINEERING
2014年
21期
153-155,158
,共4页
MAX118%FPGA%MCU%数据采集
MAX118%FPGA%MCU%數據採集
MAX118%FPGA%MCU%수거채집
MAX118%FPGA%MCU%data acquisition
针对实际中日益明显的单片机的较慢处理速度与越来越高速的数模转换器速率不能匹配的问题,本文分析了FPGA作为控制单元的特点,在此基础上设计了一个由FPGA控制的数据采集系统。提出了系统整体设计方案,自行设计了FPGA与A/D和MCU的硬件接口电路,并对如何应用FPGA实现数据采集系统的数据采集和数据缓存的逻辑控制,给出了详细的说明。对直流信号、交流信号进行了实际采集,实验数据证明,采用这种方法可以较好满足数据采集系统的实时性、同步性的要求,也增加了系统应用的灵活性。
針對實際中日益明顯的單片機的較慢處理速度與越來越高速的數模轉換器速率不能匹配的問題,本文分析瞭FPGA作為控製單元的特點,在此基礎上設計瞭一箇由FPGA控製的數據採集繫統。提齣瞭繫統整體設計方案,自行設計瞭FPGA與A/D和MCU的硬件接口電路,併對如何應用FPGA實現數據採集繫統的數據採集和數據緩存的邏輯控製,給齣瞭詳細的說明。對直流信號、交流信號進行瞭實際採集,實驗數據證明,採用這種方法可以較好滿足數據採集繫統的實時性、同步性的要求,也增加瞭繫統應用的靈活性。
침대실제중일익명현적단편궤적교만처리속도여월래월고속적수모전환기속솔불능필배적문제,본문분석료FPGA작위공제단원적특점,재차기출상설계료일개유FPGA공제적수거채집계통。제출료계통정체설계방안,자행설계료FPGA여A/D화MCU적경건접구전로,병대여하응용FPGA실현수거채집계통적수거채집화수거완존적라집공제,급출료상세적설명。대직류신호、교류신호진행료실제채집,실험수거증명,채용저충방법가이교호만족수거채집계통적실시성、동보성적요구,야증가료계통응용적령활성。
Increasingly significant for the actual obvious MCU slower processing speed and more high-speed digital to analog converter's rate can not match. For this problem, the characteristics of FPGA as the control unit is analyzed and a data acquisition system controlled by FPGA is designed in this paper. Overall system design is proposed, the hardware interface circuit between FPGA and A/D is independent designed, and gives a detailed description on how to use FPGA data to carry out the data acquisition of data acquisition system and logic control of data cache. For the actual acquisition to DC signal and AC signal, The results shows that this approach can better meet the real time and synchronization requirements of data acquisition system, but also increase the application flexibility of the system.