CAJ | 학술논문

针对高速实时图像处理系统数据量大、算法复杂度高等特点，从系统的处理性能、缓存容量、传输带宽三个要点考虑，设计了一种基于FPGA+4DSP架构的实时图像并行处理系统，使用SRIO互连技术取代传统EMIF方式实现DSP间、DSP与FPGA中间的数据传输。实验结果表明，系统传输带宽峰值为312.5 MB/s，这种新的嵌入式实时图像处理平台能够实时采集传输处理1k1k@100 f/s高分辨率图像数据，并且具有可靠性高、通用性强、灵活性好的优点。
침대고속실시도상처리계통수거량대、산법복잡도고등특점，종계통적처이성능、완존용량、전수대관삼개요점고필，설계료일충기우FPGA+4DSP가구적실시도상병행처리계통，사용SRIO호련기술취대전통EMIF방식실현DSP간、DSP여FPGA중간적수거전수。실험결과표명，계통전수대관봉치위312.5 MB/s，저충신적감입식실시도상처리평태능구실시채집전수처리1k1k@100 f/s고분변솔도상수거，병차구유가고성고、통용성강、령활성호적우점。
The high-speed real-time usually has a huge number of data with intricate algorithms;therefore it is difficult to transmit the image data real-timely in the real-system. It is that acquisition speed and transmission speed and memory capability must be considered. In the traditional method, the image data is usually capture and transport through parallel interfaces, which possess lager areas and pins in the resource limited embedded system. A new platform of image processing system is advanced based on the Serial RapidIO(SRIO)interface with one Xilinx’s FPGA chip XC5VSX50T and four TI’s DSP chip TMS320C6455. The system can real-timely transmit the image data at a high very speed of 3.125 MB/s. Since its stability, portability and feasibility has been tested, the system can service as a reference model for such a real-time image processing system designs.