湖南大学学报(自然科学版)
湖南大學學報(自然科學版)
호남대학학보(자연과학판)
JOURNAL OF HUNAN UNIVERSITY(NATURAL SCIENCES EDITION)
2014年
10期
91-95
,共5页
晏敏%徐欢%乔树山%杨红官%郑乾%戴荣新%程呈
晏敏%徐歡%喬樹山%楊紅官%鄭乾%戴榮新%程呈
안민%서환%교수산%양홍관%정건%대영신%정정
调制器%频率合成器%MASH1-1-1%流水线技术%CMOS
調製器%頻率閤成器%MASH1-1-1%流水線技術%CMOS
조제기%빈솔합성기%MASH1-1-1%류수선기술%CMOS
modulator%frequency synthesizer%MASH%pipelining technique%CMOS
介绍了一种应用于小数分频频率合成器的Σ-Δ调制器的设计,该调制器采用三阶级联的MASH1-1-1结构,并利用流水线技术,提高了调制器的工作频率.电路设计采用Verilog HDL硬件描述语言实现,基于 QuartusⅡ工具进行测试验证,结果表明,调制器最高工作频率为240.56 MHz.最终采用 SMIC 0.18μm CMOS 工艺,完成了电路版图设计.芯片面积为34148.5μm2,芯片总功耗为1.284 mW,与传统设计相比,面积降低了31.23%,功耗降低了46.14%.
介紹瞭一種應用于小數分頻頻率閤成器的Σ-Δ調製器的設計,該調製器採用三階級聯的MASH1-1-1結構,併利用流水線技術,提高瞭調製器的工作頻率.電路設計採用Verilog HDL硬件描述語言實現,基于 QuartusⅡ工具進行測試驗證,結果錶明,調製器最高工作頻率為240.56 MHz.最終採用 SMIC 0.18μm CMOS 工藝,完成瞭電路版圖設計.芯片麵積為34148.5μm2,芯片總功耗為1.284 mW,與傳統設計相比,麵積降低瞭31.23%,功耗降低瞭46.14%.
개소료일충응용우소수분빈빈솔합성기적Σ-Δ조제기적설계,해조제기채용삼계급련적MASH1-1-1결구,병이용류수선기술,제고료조제기적공작빈솔.전로설계채용Verilog HDL경건묘술어언실현,기우 QuartusⅡ공구진행측시험증,결과표명,조제기최고공작빈솔위240.56 MHz.최종채용 SMIC 0.18μm CMOS 공예,완성료전로판도설계.심편면적위34148.5μm2,심편총공모위1.284 mW,여전통설계상비,면적강저료31.23%,공모강저료46.14%.
This paper presented a design and implementation study of a three-order all-digital MASHΣ-Δmodulator,which can be used in Fractional-N Frequency Synthesizer applications.To achieve the de-sired operation frequency while providing low-power dissipation and small area,the pipelining technique was utilized in the design.The circuit was described by using the Verilog hardware description language, and the operating frequency of the modulator is 240.56 MHz based on QuartusⅡ.Eventually,the SMIC 0.18μm CMOS process was adopted,and the circuit layout was completed.The chip's area is 34148.5μm2 ,and the total power of the chip is 1.28 mW.Compared with traditional design,it can result in a 31. 23% area reduction and 46.14% power reduction.