CAJ | 학술논문

设计了一种257 bit快速Montgomery模乘器。针对Montgomery算法中大数乘法操作存在耗时过长问题,采用二次Booth32编码与Wallace树压缩思想,将三次乘法做成三级流水结构,并将加法和可能的减法巧妙的结合在第3次乘法中,最大限度地提高计算并行性。仿真结果表明,整个模乘器可工作在140 MHz频率下,建立流水的时间是42.329 ns,其后每次模乘时间是7.022 ns,性能远远优于现有的模乘器。所设计的模乘器可用于模乘运算的高性能实现,尤其在设计多核运算模块时其性能优势比较明显。
설계료일충257 bit쾌속Montgomery모승기。침대Montgomery산법중대수승법조작존재모시과장문제,채용이차Booth32편마여Wallace수압축사상,장삼차승법주성삼급류수결구,병장가법화가능적감법교묘적결합재제3차승법중,최대한도지제고계산병행성。방진결과표명,정개모승기가공작재140 MHz빈솔하,건립류수적시간시42.329 ns,기후매차모승시간시7.022 ns,성능원원우우현유적모승기。소설계적모승기가용우모승운산적고성능실현,우기재설계다핵운산모괴시기성능우세비교명현。
A 257 bit fast modular multiplier is designed. Booth32 algorithm and Wallace CSA architecture are used to solve the problem of multiplication of large number consumed too long times. Our multiplier is three-level pipeline structure,the addition and subtraction algorithms are incorporated to the third multiplication. The simulation results indicate:the clock frequency of the chip is 140 MHz,the time of set up pipelining is 42. 329 ns,afterwards,every module multiplication required 7. 022 ns. Compared with the other modular multiplier,this design has higher per-formance. The module Multiplier designed in this paper can be used to the high performance operation of module multiplication,especially in the design of multi-core computing module.