CAJ | 학술논문

ARM11核心板属于高速电路板,在设计中需要降低电源配送网络( Power Delivery Network)的输入阻抗来提高电源完整性。基于有限元方法对10个晶体管产生的同步开关噪声( Simultaneous Switching Noise)、调整前后PDN的直流/交流特性进行仿真,仿真结果表明：10个晶体管同时开关时芯片电源电压波动达7.9%；1.2 V PDN的直流电压从1.17 V增加到1.18 V,PDN的电流密度整体得到降低；在397 MHz谐振频率处PDN的谐振现象得到减弱；因此当达到10个晶体管同时开关时芯片电源电压已不满足要求,在对PDN调整后最终降低了PDN的输入阻抗和电压波动。
ARM11핵심판속우고속전로판,재설계중수요강저전원배송망락( Power Delivery Network)적수입조항래제고전원완정성。기우유한원방법대10개정체관산생적동보개관조성( Simultaneous Switching Noise)、조정전후PDN적직류/교류특성진행방진,방진결과표명：10개정체관동시개관시심편전원전압파동체7.9%；1.2 V PDN적직류전압종1.17 V증가도1.18 V,PDN적전류밀도정체득도강저；재397 MHz해진빈솔처PDN적해진현상득도감약；인차당체도10개정체관동시개관시심편전원전압이불만족요구,재대PDN조정후최종강저료PDN적수입조항화전압파동。
ARM11 core board belongs to high-speed circuit board,and during the design we need to reduce input impedance of PDN ( Power Delivery Network ) to improve power integrity. SSN ( Simultaneous Switching Noise ) produced by 10 transistors and DC/AC Characteristics of PDN before and after adjustment are simulated based on FEM,the simulation results indicate that chip power voltage fluctuation reaches 7. 9% when 10 transistors switch simultaneously;DC voltage of 1. 2 V PDN is increased from 1. 17 V to 1. 18 V,current density of PDN is reduced integrally;Resonance phenomenon of PDN is weakened at the frequency of 397 MHz;So chip power voltage hasn't satisfied the requirements when 10 transistors switch simultaneously,after PDN is adjusted,the input impedance and voltage fluctuation of PDN is reduced finally.