电子器件
電子器件
전자기건
JOURNAL OF ELECTRON DEVICES
2014年
3期
403-407
,共5页
模拟电路设计%基准电流源%带隙基准%DDS%电流舵DAC
模擬電路設計%基準電流源%帶隙基準%DDS%電流舵DAC
모의전로설계%기준전류원%대극기준%DDS%전류타DAC
analog circuit design%reference current source%bandgap reference%DDS%current-steering DAC
介绍一种用于高速DDS中电流舵DAC的带隙基准电流源电路,在传统带隙基准源电路的基础上将产生△VBE的两个三极管基极相连,使用两个运放分别将其集电极与基极钳至于相同电位,在保证三极管处于饱和区的基础上消除传统基准电路中由运放失调带来的误差VOS,通过温度补偿电路,补偿VBE与温度T的非线性项。电路采用0.18μm的深N阱1P5M工艺,选用NPN型三极管,仿真结果表明tt条件下基准电压输出温漂系数抑10×10-9/℃,基准电流输出温漂系数抑10×10-9/℃。
介紹一種用于高速DDS中電流舵DAC的帶隙基準電流源電路,在傳統帶隙基準源電路的基礎上將產生△VBE的兩箇三極管基極相連,使用兩箇運放分彆將其集電極與基極鉗至于相同電位,在保證三極管處于飽和區的基礎上消除傳統基準電路中由運放失調帶來的誤差VOS,通過溫度補償電路,補償VBE與溫度T的非線性項。電路採用0.18μm的深N阱1P5M工藝,選用NPN型三極管,倣真結果錶明tt條件下基準電壓輸齣溫漂繫數抑10×10-9/℃,基準電流輸齣溫漂繫數抑10×10-9/℃。
개소일충용우고속DDS중전류타DAC적대극기준전류원전로,재전통대극기준원전로적기출상장산생△VBE적량개삼겁관기겁상련,사용량개운방분별장기집전겁여기겁겸지우상동전위,재보증삼겁관처우포화구적기출상소제전통기준전로중유운방실조대래적오차VOS,통과온도보상전로,보상VBE여온도T적비선성항。전로채용0.18μm적심N정1P5M공예,선용NPN형삼겁관,방진결과표명tt조건하기준전압수출온표계수억10×10-9/℃,기준전류수출온표계수억10×10-9/℃。
A reference current source circuit for the current-steering DAC in the high speed DDS( Digital Direct Fre-quency Synthesis)was introduced,as foundation of the traditional reference current source circuit,the base of the two triodes were connected which produced the△VBE ,and then two amplifiers,were added to make the collector and the base clamp at the same potential. So the transistors in the condition of the saturation region to delete the error Vos that caused by the offset of the amplifiers. The VOS was eliminated in the reference current source circuit. In addition,a circuit for compensating the nonlinear term that is in the expression of VBE to T is proposed. Fabricated by 0. 18 μm N-wells 1P5M process,the NPN type triodes were used. Results showed that in the condition of tt,the tem-perature coefficient of reference output voltage was 10í10-9/℃, the temperature coefficient of reference output current was 10í10-9/℃.