CAJ | 학술논문

使用化学机械抛光（CMP）的方式，对商用芯片进行拆解，获得了不同制造工艺的铜/低 k 介质互连结构样品。通过对所获得的32 nm制造工艺的铜/低k介质互连结构样品进行进一步的化学机械抛光实验来研究抛光过程中出现的损伤。实验结果发现，抛光压力过大和过小分别会造成宏观缺陷和导线腐蚀，互连线的分布会导致导线自身的碟型缺陷、不同图案布线结构交界两侧明显的表面高度差异以及同一图案布线结构内部的表面周期性高度起伏。这种表面高度差异可以通过预补偿的方式得到一定的改善。
사용화학궤계포광（CMP）적방식，대상용심편진행탁해，획득료불동제조공예적동/저 k 개질호련결구양품。통과대소획득적32 nm제조공예적동/저k개질호련결구양품진행진일보적화학궤계포광실험래연구포광과정중출현적손상。실험결과발현，포광압력과대화과소분별회조성굉관결함화도선부식，호련선적분포회도치도선자신적설형결함、불동도안포선결구교계량측명현적표면고도차이이급동일도안포선결구내부적표면주기성고도기복。저충표면고도차이가이통과예보상적방식득도일정적개선。
Some commercial CPU chips were disassembled with the chemical mechanical polishing (CMP) method to achieve Cu/low-k interconnect structures with different manufacturing techniques. The Cu/low-k interconnect structures with manufacturing technique of 32 nm were polished further to study the damages occured in the chemical mechanical polishing process. The results show that the larger and smaller polishing pressures lead to the macroscopic defects and wire erosions separately. In addition, wiring pattern distribution would result in the dishing effects of wires, the obvious difference in surface height at the sides of different wiring pattern joints and the surface height changing in periods of the same wiring pattern, this surface height difference would be improved with the pre-offset method.