CAJ | 학술논문

针对芯片内建自测试的功耗问题，通过优化测试向量排序来实现低功耗测试。采用遗传演化思想，从减少被测电路内部节点电平翻转和自动测试向量生成电路的电平翻转两方面实现目标优化，并设计了相应的测试向量编码、目标函数、适应度函数、遗传算子和遗传算法。通过对ISCAS85和IS?CAS89基准电路的仿真测试结果证明，本文的方法比目前典型的低功耗测试方法在电平翻转数上减少了10%~33%，从而能够进一步降低测试功耗。
침대심편내건자측시적공모문제，통과우화측시향량배서래실현저공모측시。채용유전연화사상，종감소피측전로내부절점전평번전화자동측시향량생성전로적전평번전량방면실현목표우화，병설계료상응적측시향량편마、목표함수、괄응도함수、유전산자화유전산법。통과대ISCAS85화IS?CAS89기준전로적방진측시결과증명，본문적방법비목전전형적저공모측시방법재전평번전수상감소료10%~33%，종이능구진일보강저측시공모。
For power dissipation of BIST on chip, optimization for test vector sequence is researched to achieve low power dissipation test. Genetic Algorithm is used to achieve double-objective optimization which reducing jumps both from circuit-under-test and ATPG circuit. Corresponding vector code for test is designed, as well as object function, fitness function, genetic operator and genetic algorithm. Experiments on bench mark circuits such as ISCAS85 and ISCAS89 confirmed that jumps is reduced 10%-33% and power dissipation during test could be reduced more by adopting the methods in this paper than other typical methods.