CAJ | 학술논문

片上网络(NoC)被称为是能够从根本上解决复杂片上系统通信瓶颈问题的通信架构.随着VLSI工艺从亚微米、深亚微米到纳米的不断发展,使得NoC芯片设计成为可能.使用VHDL硬件描述语言完成了一款4×4 NoC 芯片的设计.芯片功能的FPGA的验证结果表明,该芯片在100 MHz系统时钟情况下工作正常,证明了设计的正确性.同时,基于180 nm HJTC 工艺库完成了该款NoC芯片的物理设计.
편상망락(NoC)피칭위시능구종근본상해결복잡편상계통통신병경문제적통신가구.수착VLSI공예종아미미、심아미미도납미적불단발전,사득NoC심편설계성위가능.사용VHDL경건묘술어언완성료일관4×4 NoC 심편적설계.심편공능적FPGA적험증결과표명,해심편재100 MHz계통시종정황하공작정상,증명료설계적정학성.동시,기우180 nm HJTC 공예고완성료해관NoC심편적물리설계.
In complex System?on?Chip(SoC),the system?communication is the bottle?neck,Network?on?Chip(NoC)is re?garded as a potential communication architecture that can fundamentally conquer this difficulty. With the development of VLSI processes,from sub?micron/deep? sub?micron to nanometer,it possible to realize NoC chip. A 4 × 4 NoC chip was designed based on VHDL. The result of FPGA?based verefication shows that the chip runs excellent under 100 MHz clock,which verifies the correctness of this design. Based on 180 nm HJTC technology library,the physical design of this NoC chip was implemented.