电子技术
電子技術
전자기술
ELECTRONIC TECHNOLOGY
2013年
3期
58-61
,共4页
锁相环%整数分频%Cadence%SMIC40nm CMOS工艺
鎖相環%整數分頻%Cadence%SMIC40nm CMOS工藝
쇄상배%정수분빈%Cadence%SMIC40nm CMOS공예
PLL%integer frequency divider%Cadence%SMIC40nm CMOS process
设计了一种基于除2/除3级联技术的可编程整数分频器.通过对其结构上的修改,明显扩大了分频比范围.同时利用在高频段采用电流模式逻辑(CML)结构和在低频段采用改进的真单相时钟(TSPC)结构进行分频,提高了分频器的工作频率.最后,基于SMIC40nm CMOS工艺,采用Cadence Spectre工具进行仿真,该分频器能够在16~127的分频比范围内对频率范围为0.5~5GHz的输入信号进行正确分频,其版图面积为107×275μm.
設計瞭一種基于除2/除3級聯技術的可編程整數分頻器.通過對其結構上的脩改,明顯擴大瞭分頻比範圍.同時利用在高頻段採用電流模式邏輯(CML)結構和在低頻段採用改進的真單相時鐘(TSPC)結構進行分頻,提高瞭分頻器的工作頻率.最後,基于SMIC40nm CMOS工藝,採用Cadence Spectre工具進行倣真,該分頻器能夠在16~127的分頻比範圍內對頻率範圍為0.5~5GHz的輸入信號進行正確分頻,其版圖麵積為107×275μm.
설계료일충기우제2/제3급련기술적가편정정수분빈기.통과대기결구상적수개,명현확대료분빈비범위.동시이용재고빈단채용전류모식라집(CML)결구화재저빈단채용개진적진단상시종(TSPC)결구진행분빈,제고료분빈기적공작빈솔.최후,기우SMIC40nm CMOS공예,채용Cadence Spectre공구진행방진,해분빈기능구재16~127적분빈비범위내대빈솔범위위0.5~5GHz적수입신호진행정학분빈,기판도면적위107×275μm.
A programmable integer frequency divider based on cascade technology of divided-by-2 or 3 is designed, in which its structure is modified, so that the range of frequency division ratio is significantly broaden. Moreover, the divider is designed with CML architecture in highband and with TSPC architecture which is improved in low-band, so that the operating frequency is improved. Finally, based on SMIC40nm CMOS process, the tool of Cadence Spectre is employed in the design to implement the simulation. It can correctly divide at 0.5GHz to 5GHz with the division ratio of 16 to 127 and its domain territory is 107×275μm.
