现代电子技术
現代電子技術
현대전자기술
MODERN ELECTRONICS TECHNIQUE
2013年
9期
144-146
,共3页
刘云康%彭晓宏%胡勇%侯立刚%朱志鼎%吕本强
劉雲康%彭曉宏%鬍勇%侯立剛%硃誌鼎%呂本彊
류운강%팽효굉%호용%후립강%주지정%려본강
折叠式共源共栅%增益提高技术%运算放大器%低电压电流镜
摺疊式共源共柵%增益提高技術%運算放大器%低電壓電流鏡
절첩식공원공책%증익제고기술%운산방대기%저전압전류경
folded cascode%gain boosting technology%operational amplifier%low?voltage current mirror
基于chartered 0.35μm工艺,采用PMOS管作为输入管的折叠式共源共栅结构,设计了一种采用增益提高技术的两级运算放大器.利用Cadence公司的spectre对电路进行仿真,该电路在3.3 V电源电压下具有125.8 dB的直流开环增益,2.43 MHz的单位增益带宽,61.2°的相位裕度,96.3 dB的共模抑制比.
基于chartered 0.35μm工藝,採用PMOS管作為輸入管的摺疊式共源共柵結構,設計瞭一種採用增益提高技術的兩級運算放大器.利用Cadence公司的spectre對電路進行倣真,該電路在3.3 V電源電壓下具有125.8 dB的直流開環增益,2.43 MHz的單位增益帶寬,61.2°的相位裕度,96.3 dB的共模抑製比.
기우chartered 0.35μm공예,채용PMOS관작위수입관적절첩식공원공책결구,설계료일충채용증익제고기술적량급운산방대기.이용Cadence공사적spectre대전로진행방진,해전로재3.3 V전원전압하구유125.8 dB적직류개배증익,2.43 MHz적단위증익대관,61.2°적상위유도,96.3 dB적공모억제비.
Based on Chartered 0.35 μm process,a two?stage operational amplifier with gain boosting technology was de?signed by using the PMOS transistor as the folded?cascode structure of the input tube. The circuit was simulated by Spectre made in Cadence. The circuit at 3.3 V has DC open?loop gain of 125.8 dB,unity?gain bandwidth of 2.43 MHz,phase margin of 61.2°,CMRR of 96.3 dB.
