CAJ | 학술논문

本文提出了一种新型高速均衡电路.在传统源极负反馈均衡滤波结构的基础上改进电路结构,使用有源电感及对称负载结构改善了电路性能,避免了使用片上电感,优化了电路结构,节省了芯片面积,同时缓解了传统均衡电路的速度瓶颈.经仿真验证,该均衡器电路高频补偿增益达到17.2dB ,高低频增益比达到5.24,信号速率达到5Gb/s 时能完整接收信号,实现均衡效果.该电路结构简单,适用于各种高速信号接口电路.该电路采用0.13μm CMOS 工艺实现.
본문제출료일충신형고속균형전로.재전통원겁부반궤균형려파결구적기출상개진전로결구,사용유원전감급대칭부재결구개선료전로성능,피면료사용편상전감,우화료전로결구,절성료심편면적,동시완해료전통균형전로적속도병경.경방진험증,해균형기전로고빈보상증익체도17.2dB ,고저빈증익비체도5.24,신호속솔체도5Gb/s 시능완정접수신호,실현균형효과.해전로결구간단,괄용우각충고속신호접구전로.해전로채용0.13μm CMOS 공예실현.
@@@@This paper presents a new type of high - speed equalization circuit .On the basis of the traditional source degeneration equalization filter ,a new equalization circuit structure is proposed .The circuit performance is greatly improved with the advantages of active inductor and symmetric load structure .Without using on - chip inductors , the new structure optimizes the circuit , saves chip area , while alleviates the speed bottleneck of the traditional equalization circuit .Judging by simulation results ,the high frequency compensation gain of the equalizer circuit is up to 17 .2dB ,meanwhile ,the ratio of high frequency to low frequency is 5 .24 .The circuit operates functionally when signal speed rates up to 5Gbit/s .The circuit topology is simple ,and applicable to a variety of high - speed interface circuit .This chip is realized in 0 .13μm CMOS process .