CAJ | 학술논문

分析了在三相电压不对称情况下传统软件锁相环相位输出产生误差的原因,提出一个改进的单同步坐标变换软件锁相环方法,即通过αβ坐标变换,并延迟 T/4周期计算来实现正、负序分量的分离,跟踪三相电压的正序分量以减小误差.基于 RTDS 搭建了 MMC-HVDC 一次系统模型,将改进软件锁相环应用于基于 FPGA 的 MMC-HVDC 控制器上,采用相关的控制和平衡策略,能有效地调节母线电压和有功功率,说明了改进软件锁相环相位输出的准确性.
분석료재삼상전압불대칭정황하전통연건쇄상배상위수출산생오차적원인,제출일개개진적단동보좌표변환연건쇄상배방법,즉통과αβ좌표변환,병연지 T/4주기계산래실현정、부서분량적분리,근종삼상전압적정서분량이감소오차.기우 RTDS 탑건료 MMC-HVDC 일차계통모형,장개진연건쇄상배응용우기우 FPGA 적 MMC-HVDC 공제기상,채용상관적공제화평형책략,능유효지조절모선전압화유공공솔,설명료개진연건쇄상배상위수출적준학성.
Analyzing the phase output deviation cause of traditional software phase-locked loop (SPLL) under three-phase asymmetrical voltage, this paper puts forward an improved SPLL model using αβ coordinate transform and T/4 shift calculation to realize the separation of the positive and negative sequence components and to track the positive one as to reduce the deviation. Modeling the primary system of modular multilevel converter based HVDC(MMC-HVDC)in RTDS, and using the improved SPLL to the MMC-HVDC controller based on FPGA, and adopting related control and balance strategies, it proves that the controller can effectively adjust the bus voltage and active power, showing that the accuracy of phase output with the improved SPLL is very good.