CAJ | 학술논문

传统集成电路制造工艺主要采用铝作为金属互连材料,但是随着晶体管尺寸越来越小,在0.13μm及以上制程中,一般采用铜大马士革互连工艺来提高器件的可靠性.铜互连工艺中需要用氮化硅作为穿孔图形蚀刻的阻挡层,由于氮化硅材质具有很强的应力,再加上制程中的热反应和蚀刻效应就会造成氮化硅层从界面掀起从而形成一种鼓包状缺陷(bubble defect).文章通过调整并控制铜金属连线层间氧化电介质层的蚀刻速率,改变有机介质层(BARC)的沉积方法,以及改进产品的电路设计的检验规则,从而解决鼓包状缺陷的产生,降低产品芯片的报废率,提高产品的良率.
전통집성전로제조공예주요채용려작위금속호련재료,단시수착정체관척촌월래월소,재0.13μm급이상제정중,일반채용동대마사혁호련공예래제고기건적가고성.동호련공예중수요용담화규작위천공도형식각적조당층,유우담화규재질구유흔강적응력,재가상제정중적열반응화식각효응취회조성담화규층종계면흔기종이형성일충고포상결함(bubble defect).문장통과조정병공제동금속련선층간양화전개질층적식각속솔,개변유궤개질층(BARC)적침적방법,이급개진산품적전로설계적검험규칙,종이해결고포상결함적산생,강저산품심편적보폐솔,제고산품적량솔.
The traditional IC manufacturing technology mainly using AL line as interconnect material, but when the line width of transistor getting smaller and smaller, in 0.13μm technology and above, now use Cu damascene interconnect to improve the device reliability. SIN film works as the etch stop layer in Cu interconnect technology, high stress combined with the thermal and etch effects in the process, induced SIN peeling from the IMD film and form the bubble defect. This article describes three solutions:modify and control IMD layer etch rate, change BARC deposition method from one step to two step, and add the design rule check for new product tape out, these three methods can avoid the occurrence of bubble defect, thus reduce the wafer scrap rate and improve the product yield.