CAJ | 학술논문

为满足医学系统芯片(SOC)的低成本、低功耗、微型化的需求,定制了一款兼容 AHB总线接口的 Nor Flash控制器IP .该设计针对常规Flash控制器功能繁杂,读写数据需长时间等待等缺点,采用了硬件解锁、简化块擦除模块和增加写操作数据寄存器等优化设计方法.该设计最后进行了FPGA原型验证并进行了流片,验证测试结果表明,该IP功能正确,总线的利用率得到了提高.在系统时钟10 M Hz下,选用S29LV008J Nor Flash芯片,按连续存储16个32位数据计算,本设计比常规设计减少总线占用时间165μs ,设计达到了预期结果.
위만족의학계통심편(SOC)적저성본、저공모、미형화적수구,정제료일관겸용 AHB총선접구적 Nor Flash공제기IP .해설계침대상규Flash공제기공능번잡,독사수거수장시간등대등결점,채용료경건해쇄、간화괴찰제모괴화증가사조작수거기존기등우화설계방법.해설계최후진행료FPGA원형험증병진행료류편,험증측시결과표명,해IP공능정학,총선적이용솔득도료제고.재계통시종10 M Hz하,선용S29LV008J Nor Flash심편,안련속존저16개32위수거계산,본설계비상규설계감소총선점용시간165μs ,설계체도료예기결과.
@@@@To meet the demand for low power ,low‐cost and miniaturization of the medical system‐on‐chip (SOC) ,a AHB bus compatible Nor Flash controller IP was designed .The optimal design methods of simplifying the sector erase module ,increasing the write data register and hardware unlock were adopted to overcome the disadvantageous of conventional Flash controller ,such as the complicated logical design ,long waiting time for reading and writing . The design was verified by FPGA and taped out finally ,the verified results show that the function of the IP was correct and the bus utilization has been improved .When the system ran at 10M Hz and the S29LV008J chip was selected ,the bus utilization time was reduced 165μs when sixteen 32 bit data were stored continuously .