CAJ | 학술논문

基于延迟锁相环原理,提出了一种新型的具有延迟校准功能的可编程多相位时钟电路,能为工作在80 MHz的电荷耦合器件信号处理器提供精度高达390 ps的时序信号.将主时钟的单周期等分为32份,通过可编程相位组合电路,产生相位及占空比可调的信号,能满足不同电荷耦合器件所需的最优工作时序.传统的延迟锁相环结构随着延迟单元的增加,延迟单元之间不匹配愈加明显,导致输出相位偏离理想位置.引入延迟校准电路可以显著降低相位之间的误差,校准后的多相位时钟信号接入可编程相位组合器进行选择组合,产生所需的高精度时序信号.基于 SMIC 0.18μm 3.3 V CMOS工艺完成设计,在80 MHz主时钟下的后仿真结果表明：电路可产生占空比范围为2%~98%的输出时钟,校准后的延迟误差小于5 ps,边到边抖动为1.14 ps,有效地保证了相位精度.
기우연지쇄상배원리,제출료일충신형적구유연지교준공능적가편정다상위시종전로,능위공작재80 MHz적전하우합기건신호처리기제공정도고체390 ps적시서신호.장주시종적단주기등분위32빈,통과가편정상위조합전로,산생상위급점공비가조적신호,능만족불동전하우합기건소수적최우공작시서.전통적연지쇄상배결구수착연지단원적증가,연지단원지간불필배유가명현,도치수출상위편리이상위치.인입연지교준전로가이현저강저상위지간적오차,교준후적다상위시종신호접입가편정상위조합기진행선택조합,산생소수적고정도시서신호.기우 SMIC 0.18μm 3.3 V CMOS공예완성설계,재80 MHz주시종하적후방진결과표명：전로가산생점공비범위위2%~98%적수출시종,교준후적연지오차소우5 ps,변도변두동위1.14 ps,유효지보증료상위정도.
Based on the principle of the delay-locked loop (DLL),this paper introduces a programmable multi-phase clock circuit with a delay calibration loop.The proposed circuit offers a clock signal with a precision of 390 ps and optimum timing for a variety of CCD signal processors.One cycle of the main clock is divided into 32 parts equally,while timing with a tunable duty cycle is generated by the programmable phase combiner.The increase in delay elements worsens the delay time error between different phases of the output signals,and hence a delay time calibration loop is applied to suppress this effect.In SMIC 0.1 8μm 3.3 V CMOS process,with a 80 MHz main clock,the post simulation results show that the proposed circuit generates an output clock with a 2%~98% duty cycle,a 1.14 ps edge to edge jitter and a less than 5 ps calibrated delay time error.