CAJ | 학술논문

针对图形处理器三维引擎中对图形的后期处理需求，实现片段写入帧缓冲区前的测试、混合、逻辑操作、累积、清除和屏蔽等关键功能。分析并提取了OpenGL核心库中的片段处理相关函数，确定了片段处理单元要实现的功能；合理安排多个片段处理功能的执行顺序，设计了基于流水线的片段处理单元结构；采用Verilog HDL对电路进行描述，采用 Cadence NC-Verilog 仿真工具进行虚拟验证，采用 Xilinx 的 ISE 工具进行综合，并在 Xilinx Virtex6 XC6VLX760 FPGA上进行原型验证，电路工作频率可以达到180 MHz，测试功能正确。在SMIC 65 nm CMOS工艺下，采用Synopsys Design-Compiler对设计进行综合，电路工作频率达到300 MHz，满足设计需求。
침대도형처리기삼유인경중대도형적후기처리수구，실현편단사입정완충구전적측시、혼합、라집조작、루적、청제화병폐등관건공능。분석병제취료OpenGL핵심고중적편단처리상관함수，학정료편단처리단원요실현적공능；합리안배다개편단처리공능적집행순서，설계료기우류수선적편단처리단원결구；채용Verilog HDL대전로진행묘술，채용 Cadence NC-Verilog 방진공구진행허의험증，채용 Xilinx 적 ISE 공구진행종합，병재 Xilinx Virtex6 XC6VLX760 FPGA상진행원형험증，전로공작빈솔가이체도180 MHz，측시공능정학。재SMIC 65 nm CMOS공예하，채용Synopsys Design-Compiler대설계진행종합，전로공작빈솔체도300 MHz，만족설계수구。
In view of the post-processing requirements of graphics on three-dimensional ( 3D ) engine in Graphic Processing Unit ( GPU) , a series of key functions such as the test, blend, logic operation, accumulating, clear, mask are implemented before fragments are written into the frame buffer. The relative functions of fragment operation were analyzed and extracted from the OpenGL core library, and then the realized functions of Fragment Operation Unit ( FOU) were confirmed. Based on reasonable arrangement of work orders for the different fragment operation functions, a unit structure for FOU was designed. Further, hardware circuit was described by Verilog HDL, and functional virtual verification was accomplished by Cadence NC-Verilog simulator. Finally, Xilinx ISE tools were used for comprehensive, and on Xilinx Virtex6 XC6VLX760 FPGA for prototype verification. As a result, the frequency of circuit operating was up to 180 MHz and the test functions were correct. In addition, the design was synthesized under SMIC 65 nm CMOS technology by Synopsys Design-Compiler. The frequency of FOU ASIC design was up to 300 MHz, which met the design requirements.