计算机应用
計算機應用
계산궤응용
COMPUTER APPLICATION
2014年
z2期
55-58
,共4页
1553B协议%双余度总线%FPGA%Verilog HDL%远程终端
1553B協議%雙餘度總線%FPGA%Verilog HDL%遠程終耑
1553B협의%쌍여도총선%FPGA%Verilog HDL%원정종단
1553B protocol%dual-redundancy bus%FPGA ( Field Programmable Gate Array)%Verilog HDL%remote terminal
为了降低1553B 节点的成本和提高应用开发的灵活性，设计并实现一种基于现场可编辑逻辑器件（FPGA）的1553B总线的远程终端系统。首先根据1553B总线协议和远程终端在整个总线中的功能进行了模块的划分，然后用Verilog HDL硬件描述语言对各个功能模块进行了实现，并使用Modelsim-altera 软件对各个模块的功能进行了仿真。最后通过quartus 13.0生成下载文件，下载至板卡上进行测试，结果显示1553B总线远程终端满足项目要求的各项性能指标。
為瞭降低1553B 節點的成本和提高應用開髮的靈活性，設計併實現一種基于現場可編輯邏輯器件（FPGA）的1553B總線的遠程終耑繫統。首先根據1553B總線協議和遠程終耑在整箇總線中的功能進行瞭模塊的劃分，然後用Verilog HDL硬件描述語言對各箇功能模塊進行瞭實現，併使用Modelsim-altera 軟件對各箇模塊的功能進行瞭倣真。最後通過quartus 13.0生成下載文件，下載至闆卡上進行測試，結果顯示1553B總線遠程終耑滿足項目要求的各項性能指標。
위료강저1553B 절점적성본화제고응용개발적령활성，설계병실현일충기우현장가편집라집기건（FPGA）적1553B총선적원정종단계통。수선근거1553B총선협의화원정종단재정개총선중적공능진행료모괴적화분，연후용Verilog HDL경건묘술어언대각개공능모괴진행료실현，병사용Modelsim-altera 연건대각개모괴적공능진행료방진。최후통과quartus 13.0생성하재문건，하재지판잡상진행측시，결과현시1553B총선원정종단만족항목요구적각항성능지표。
In order to reduce the cost of the 1553B remote node and improve the flexibility of the application and development, a 1553B bus remote terminal based on FPGA ( Field Programmable Gate Array) was designed and implemented in the paper. Firstly, according to the protocols of 1553B bus and the function of the remote terminal in the bus system, the system was divided into several modules. Then all the functional modules were realized by Verilog HDL, and simulated with Modelsim-altera software. The result of testing on the board shows that the performances meet the design requirement.
