CAJ | 학술논문

基于模拟退火的现场可编程门阵列( FPGA )布局算法在计算关键度时存在一定的偏差。为此，提出一种FPGA布局时延改进算法。利用不同的模拟退火温度和交换接收率，以及前后2次布局的时延代价差，对FPGA布局的时延代价进行补偿。通过增加时延补偿模块来调整布局的代价函数，达到重新寻找布局过程中被遗弃的较优解的目的。实验结果表明，在MCNC基准电路上使用改进算法，布局的时延代价和线网代价分别比改进前的算法减少19.2%和0.5%。此外，电路的关键路径时延也得到了不同程度的改善，使得布局质量在各个方面都明显优于优化前的通用布局布线算法。
기우모의퇴화적현장가편정문진렬( FPGA )포국산법재계산관건도시존재일정적편차。위차，제출일충FPGA포국시연개진산법。이용불동적모의퇴화온도화교환접수솔，이급전후2차포국적시연대개차，대FPGA포국적시연대개진행보상。통과증가시연보상모괴래조정포국적대개함수，체도중신심조포국과정중피유기적교우해적목적。실험결과표명，재MCNC기준전로상사용개진산법，포국적시연대개화선망대개분별비개진전적산법감소19.2%화0.5%。차외，전로적관건로경시연야득도료불동정도적개선，사득포국질량재각개방면도명현우우우화전적통용포국포선산법。
There is some degree of error during the calculation of the critical in Field Programmable Gate Array ( FPGA) placement algorithm based on simulated annealing. In order to solve this problem, a new FPGA placement algorithm is proposed. The improved algorithm can find a better placement that is discarded previously by adding a delay compensation module which leverages the information such as the different annealing temperature, the every exchange success rate under different temperatures,and the difference of delay cost between two successive placements. The new algorithm is implemented and tested on several MCNC benchmark circuits. Experimental results show that,the delay cost and the wire cost are reduced by 19. 2% and 0. 5% . Besides,the critical path delay of the circuits is improved at different levels,thus making the quality of placement significantly higher than the original Versatile Place and Route ( VPR ) placement algorithm.