CAJ | 학술논문

随着集成电路工艺进入微纳尺度，组合逻辑电路的软错误率不断增加，电路的可靠性受到严重威胁。传统的逻辑门加固结构通常会带来较大的面积开销。文章采用具有鲁棒容错性能的级联电压开关逻辑（cas‐cade voltage switch logic ，简称CVSL）门单元，提出“CVSL门对”结构对电路输出端进行选择性加固，以较小面积开销实现电路容错性能的大幅提升。Hspice仿真实验表明“CVSL门对”结构具有良好的容忍故障脉冲性能。ISCAS‐89基准电路实验结果表明，被加固电路软错误防护率达90％以上，仅带来12.54％的面积开销，比CWSP单元加固法节省46.57％，比三模冗余结构加固法节省91.78％。
수착집성전로공예진입미납척도，조합라집전로적연착오솔불단증가，전로적가고성수도엄중위협。전통적라집문가고결구통상회대래교대적면적개소。문장채용구유로봉용착성능적급련전압개관라집（cas‐cade voltage switch logic ，간칭CVSL）문단원，제출“CVSL문대”결구대전로수출단진행선택성가고，이교소면적개소실현전로용착성능적대폭제승。Hspice방진실험표명“CVSL문대”결구구유량호적용인고장맥충성능。ISCAS‐89기준전로실험결과표명，피가고전로연착오방호솔체90％이상，부대래12.54％적면적개소，비CWSP단원가고법절성46.57％，비삼모용여결구가고법절성91.78％。
With the integrated circuit technology entering micro‐nano scale ,the soft error rate of com‐binational logic circuit continues to increase ,the reliability of the circuit is under serious threat .T he traditional logic gate hardening structure usually brings large area overhead .In this paper ,the cascade voltage switch logic(CVSL) gate unit which has robust fault‐tolerance performance is utilized and the“CVSL gate pair” structure is proposed to selectively harden the outputs of circuit ,realizing big im‐provement of circuits’ fault‐tolerance performance under small area overhead .The Hspice simulation result show s that the“CVSL gate pair”structure has good fault‐tolerance pulse performance .T he ex‐perimental result of ISCAS‐89 benchmark circuits shows that the hardened circuits’ soft error rate is reduced by more than 90% ,bringing only an area overhead of 12.54% which is 46.57% lower than that of CWSP hardening scheme and 91.78% lower than that of TMR hardening scheme .