CAJ | 학술논문

详细阐述了AES算法的硬件语言实现过程，并提出了一种优化方法，在对AES算法优化的实现过程中，将密钥扩展模块与轮加模块合并实现，并结合SDK平台的控制来完成加密算法，最后，进行了FPGA硬件实现与资源利用对比实验，验证了算法的正确性和优越性。
상세천술료AES산법적경건어언실현과정，병제출료일충우화방법，재대AES산법우화적실현과정중，장밀약확전모괴여륜가모괴합병실현，병결합SDK평태적공제래완성가밀산법，최후，진행료FPGA경건실현여자원이용대비실험，험증료산법적정학성화우월성。
The process of AES algorithm was described in detail with hardware description language, and a kind of optimal meth?od was proposed. During the implemental process of AES algorithm, merging the KeyExpansion module and the AddRound?Key module,and combining with the control of the SDK platform to complete the encryption algorithm;finally, the implementa?tion and superiority was verified, the resource was contrasted by FPGA.