仪表技术与传感器
儀錶技術與傳感器
의표기술여전감기
INSTRUMENT TECHNIQUE AND SENSOR
2014年
12期
56-58
,共3页
闸门%改进的多周期同步%SOPC%NiosII%FPGA%分频
閘門%改進的多週期同步%SOPC%NiosII%FPGA%分頻
갑문%개진적다주기동보%SOPC%NiosII%FPGA%분빈
gate%improved multi-period synchronous frequency%NiosII%FPGA%frequency division
为了使得待测信号，时间基准信号与实际计数闸门同步，消除对待测信号和时间基准信号产生的±1误差，采用改进的多周期同步频率测量，利用SOPC 设计技术，以FPGA为核心，对标准脉冲信号计数，NiosⅡ软和处理器作为系统控制单元；并通过划分频率段，先粗测再精测，设置不同闸门时间，使得系统测量频率范围保证在0．1 Hz～10 MHz，兼顾了测量频率的精度，测量的高效率。
為瞭使得待測信號，時間基準信號與實際計數閘門同步，消除對待測信號和時間基準信號產生的±1誤差，採用改進的多週期同步頻率測量，利用SOPC 設計技術，以FPGA為覈心，對標準脈遲信號計數，NiosⅡ軟和處理器作為繫統控製單元；併通過劃分頻率段，先粗測再精測，設置不同閘門時間，使得繫統測量頻率範圍保證在0．1 Hz～10 MHz，兼顧瞭測量頻率的精度，測量的高效率。
위료사득대측신호，시간기준신호여실제계수갑문동보，소제대대측신호화시간기준신호산생적±1오차，채용개진적다주기동보빈솔측량，이용SOPC 설계기술，이FPGA위핵심，대표준맥충신호계수，NiosⅡ연화처리기작위계통공제단원；병통과화분빈솔단，선조측재정측，설치불동갑문시간，사득계통측량빈솔범위보증재0．1 Hz～10 MHz，겸고료측량빈솔적정도，측량적고효솔。
By using the SOPC design technology, an improved multi-period synchronous frequency was adopted in order to make the time reference signal and the actual count gate keep synchronous and eliminate the ±1 errors that were generated by the time based signal and the signal to be measured.The FPGA was the core of the standard pulse count and the NiosII soft processor was used as the system control unit.By dividing the frequency band, setting different gate times and through first rough measure-ment and then precision measurement,it was ensured that the range of measurement frequency varied from 0.1Hz to 10MHz It also satisfied the accuracy and the efficiency of the frequency measurement.
