电子科技大学学报
電子科技大學學報
전자과기대학학보
JOURNAL OF UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
2015年
1期
97-100
,共4页
李浪%邹祎%贺位位%李仁发
李浪%鄒祎%賀位位%李仁髮
리랑%추의%하위위%리인발
面积优化%EPCBC加密算法%FPGA%Verilog HDL
麵積優化%EPCBC加密算法%FPGA%Verilog HDL
면적우화%EPCBC가밀산법%FPGA%Verilog HDL
area optimization%EPCBC cipher%FPGA%Verilog HDL
针对资源约束的智能卡加密需要小面积实现的问题，对EPCBC加密算法从硬件上实现面积优化进行了如下研究：1)相同运算只实现一次，主程序调用32次完成加密；2)对S盒变换和密钥变换使用同一寄存器，从而节省寄存器数量；3)把密文轮操作和密钥更新放在一个模块中。通过FPGA优化结果表明，EPCBC密码算法实现面积大幅度减小，优化率达到56%，同时加密运算性能也没有降低，从而为开发受资源约束的智能卡密码硬件提供可行方案。
針對資源約束的智能卡加密需要小麵積實現的問題，對EPCBC加密算法從硬件上實現麵積優化進行瞭如下研究：1)相同運算隻實現一次，主程序調用32次完成加密；2)對S盒變換和密鑰變換使用同一寄存器，從而節省寄存器數量；3)把密文輪操作和密鑰更新放在一箇模塊中。通過FPGA優化結果錶明，EPCBC密碼算法實現麵積大幅度減小，優化率達到56%，同時加密運算性能也沒有降低，從而為開髮受資源約束的智能卡密碼硬件提供可行方案。
침대자원약속적지능잡가밀수요소면적실현적문제，대EPCBC가밀산법종경건상실현면적우화진행료여하연구：1)상동운산지실현일차，주정서조용32차완성가밀；2)대S합변환화밀약변환사용동일기존기，종이절성기존기수량；3)파밀문륜조작화밀약경신방재일개모괴중。통과FPGA우화결과표명，EPCBC밀마산법실현면적대폭도감소，우화솔체도56%，동시가밀운산성능야몰유강저，종이위개발수자원약속적지능잡밀마경건제공가행방안。
In order to achieve small area implementation of encryption in resource-constrained smart cards, we studied the hardware optimal implementation of electronic product code block cipher(EPCBC) encryption algorithm. Firstly, each operation is accomplished only once, and the main program calls the 32 times to complete the encryption. Secondly, the same register is used in the S-box and key transformation so that the number of required registers is reduced. Thirdly, the cipher round operation and key update are put in the same module. Through field programmable gate array(FPGA) the experimental results show that the implementation area of EPCBC is greatly reduced, the optimization efficiency rate reaches 56%, and the encryption performance is not decreased so as to provide practical solutions for resource-constrained cryptographic smart cards.
