CAJ | 학술논문

介绍了一种基于行间转移CCD KAI-04022的成像系统设计方法。成像系统采用灵活的驱动电路设计方法，利用二极管钳位及MOSFET驱动器完成了各个两电平驱动信号的设计，利用模拟前端芯片和压摆率控制电路产生垂直三电平驱动信号。模拟前端芯片AD9920A自带12位精度的A/D转换器，CCD输出的模拟信号通过它进行数字化采样，数字化的图像信号将被FPGA读入到下一级处理模块。为了解决双通道输出产生的非均匀性问题，本系统采用多点校正算法，设计了可实现的FPGA硬件校正模块，在代价较小的情况下，完成了非均匀校正功能。校正后的图像利用高速LVDS接口传输给上位机。实验证明，在像素时钟为40MHz时，成像系统的帧频可以达到16frame/s。在实验室环境下，对CCD直接进行辐照测试实验，测得图像的信噪比为33dB，成像质量满足系统的要求。
개소료일충기우행간전이CCD KAI-04022적성상계통설계방법。성상계통채용령활적구동전로설계방법，이용이겁관겸위급MOSFET구동기완성료각개량전평구동신호적설계，이용모의전단심편화압파솔공제전로산생수직삼전평구동신호。모의전단심편AD9920A자대12위정도적A/D전환기，CCD수출적모의신호통과타진행수자화채양，수자화적도상신호장피FPGA독입도하일급처리모괴。위료해결쌍통도수출산생적비균균성문제，본계통채용다점교정산법，설계료가실현적FPGA경건교정모괴，재대개교소적정황하，완성료비균균교정공능。교정후적도상이용고속LVDS접구전수급상위궤。실험증명，재상소시종위40MHz시，성상계통적정빈가이체도16frame/s。재실험실배경하，대CCD직접진행복조측시실험，측득도상적신조비위33dB，성상질량만족계통적요구。
A design method for area array-CCD KAI-04022 imaging system based on FPGA was proposed. A flexible method of the driving circuit was used to design the imaging system. The two level driving signal was generatedby the diode clamp circuit and a MOSFET driver. The three level driving signal was generated by the AFE chip and slew rate control circuit. A 12bit ADC was embedded in the AD9920A, through which the output analog signal from CCD converted to the digital signal. The digital image signal would be stored into the next level processing unit by FPGA. The multipoint correction algorithm was adopted to solve the non-uniformity resulting from the dual output channel. A realizable FPGA hardware correction unit was designed. The non-uniformity correction was accomplished under low cost. The corrected image was transmitted to PC by the interface bus of high speed LVDS.The experimental results indicated that the max frame rate of the imaging system was 16f/s,when the pixel rate was 40MHz.The signal-to-noise ratio of the image captured in the laboratory was 33dB and the image quality would meet the requirements of the system.