CAJ | 학술논문

提出了一种功耗约束下的三维堆叠集成电路（3D－SICs）测试调度优化算法。该算法在功耗约束下，协同优化了测试应用时间、TAM总线带宽和测试硬件开销。通过采用ITC’02标准电路中的d695和p93791做应用验证，结果表明该算法将测试应用时间分别减少为91.25％和93.11％，证明算法能有效地减少测试应用时间，降低测试成本。
제출료일충공모약속하적삼유퇴첩집성전로（3D－SICs）측시조도우화산법。해산법재공모약속하，협동우화료측시응용시간、TAM총선대관화측시경건개소。통과채용ITC’02표준전로중적d695화p93791주응용험증，결과표명해산법장측시응용시간분별감소위91.25％화93.11％，증명산법능유효지감소측시응용시간，강저측시성본。
This paper presented a test scheduling optimization algorithm for 3D stacked ICs under power constrains,which op-timized test application time,TAM bus bandwidth and hardware expenses collaboratively.Using d695 and p93791 of the benchmark circuits ITC'02 to verify,the experimental results show that the test application time is reduced to 91.25%and 93.11%respectively. It proves that the proposed algorithm can effectively reduce the test application time and the test cost.