计算机辅助设计与图形学学报
計算機輔助設計與圖形學學報
계산궤보조설계여도형학학보
JOURNAL OF COMPUTER-AIDED DESIGN & COMPUTER GRAPHICS
2015年
2期
256-263
,共8页
SURF算法%并行优化%硬件实现%径向梯度变换%扇形分割
SURF算法%併行優化%硬件實現%徑嚮梯度變換%扇形分割
SURF산법%병행우화%경건실현%경향제도변환%선형분할
SURF algorithm%parallel optimization%hardware implementation%radial gradient transform%fan-shaped segmentation
加速鲁棒特征(SURF)算法计算复杂度高、硬件实现需要大量的逻辑和存储资源,且描述符构建过程难以并行实现、无法满足实时性要求.针对上述问题,提出一种SURF算法的并行优化方法,并给出基于FPGA器件的硬件实现方法.首先采用圆形特征区域和径向梯度变换等方法实现旋转不变性,达到取消主方向计算和特征区域旋转的目的,实现SURF算法从积分图像计算到描述符生成的全过程并行优化;然后基于FPGA器件,采用多存储器和多路并行流水结构实时实现SURF优化算法.对比实验结果表明, SURF优化算法的匹配性能与SURF算法相当,虽然匹配点数比SURF算法低5%~20%,但匹配正确率比SURF算法高5%~10%; SURF优化算法硬件实现仅采用13.5MHz的时钟,对于分辨率为720×576的视频流,处理速度达到25帧/s,满足了实时性要求.
加速魯棒特徵(SURF)算法計算複雜度高、硬件實現需要大量的邏輯和存儲資源,且描述符構建過程難以併行實現、無法滿足實時性要求.針對上述問題,提齣一種SURF算法的併行優化方法,併給齣基于FPGA器件的硬件實現方法.首先採用圓形特徵區域和徑嚮梯度變換等方法實現鏇轉不變性,達到取消主方嚮計算和特徵區域鏇轉的目的,實現SURF算法從積分圖像計算到描述符生成的全過程併行優化;然後基于FPGA器件,採用多存儲器和多路併行流水結構實時實現SURF優化算法.對比實驗結果錶明, SURF優化算法的匹配性能與SURF算法相噹,雖然匹配點數比SURF算法低5%~20%,但匹配正確率比SURF算法高5%~10%; SURF優化算法硬件實現僅採用13.5MHz的時鐘,對于分辨率為720×576的視頻流,處理速度達到25幀/s,滿足瞭實時性要求.
가속로봉특정(SURF)산법계산복잡도고、경건실현수요대량적라집화존저자원,차묘술부구건과정난이병행실현、무법만족실시성요구.침대상술문제,제출일충SURF산법적병행우화방법,병급출기우FPGA기건적경건실현방법.수선채용원형특정구역화경향제도변환등방법실현선전불변성,체도취소주방향계산화특정구역선전적목적,실현SURF산법종적분도상계산도묘술부생성적전과정병행우화;연후기우FPGA기건,채용다존저기화다로병행류수결구실시실현SURF우화산법.대비실험결과표명, SURF우화산법적필배성능여SURF산법상당,수연필배점수비SURF산법저5%~20%,단필배정학솔비SURF산법고5%~10%; SURF우화산법경건실현부채용13.5MHz적시종,대우분변솔위720×576적시빈류,처리속도체도25정/s,만족료실시성요구.
SURF algorithm has high computational complexity, and requires a lot of logic and memory resources. Moreover the process of descriptor extraction is difficult to implement in parallel and unable to meet real-time requirements. To solve the above disadvantages, an optimized SURF algorithm is put forward and the FPGA im-plementation is also provided. A rotation invariant and fully parallel optimized SURF algorithm is achieved using circular feature region and radial gradient transform method, which cancels the processes of main direction cal-culation and feature region rotation. Then the optimized SURF algorithm is implemented based on FPGA by us-ing multi-memory and multi-channel parallel pipelined architecture. By experimental comparison, the matching performance of the optimized SURF algorithm is as good as the original SURF algorithm. Compared with the original SURF descriptor, the number of matching points reduces in 5%to 20%, but the accuracy of matching improves in 5%to 10%. The FPGA implementation of proposed SURF algorithm meets real-time requirements by using 13.5 MHz clock. For a video stream with resolution of 720×576, the processing speed reaches 25 fps.