CAJ | 학술논문

为降低成本，提高设计灵活性，提出一种基于FPGA的1553B总线接口方案；采用自顶向下的设计方法，在分析1553B总线接口工作原理和响应流程的基础上，完成了接口方案各FPGA功能模块设计；对关键模块编写VHDL代码，并采用Active?HDL软件进行了仿真；以Virtex?5 FPGA开发板和PC机为验证平台，在FPGA中分别模拟BC与RT，在PC机指令下进行了BC与RT功能模块间的收发测试，结果表明系统能在协议规定的1 MHz数据率下稳定运行；同时，为提升接口性能，采用光纤代替传统电缆传输介质，利用FPGA内嵌RocketIO内核进行了传统1553协议数据的光纤传输，速率可达3 Gb/s以上。
위강저성본，제고설계령활성，제출일충기우FPGA적1553B총선접구방안；채용자정향하적설계방법，재분석1553B총선접구공작원리화향응류정적기출상，완성료접구방안각FPGA공능모괴설계；대관건모괴편사VHDL대마，병채용Active?HDL연건진행료방진；이Virtex?5 FPGA개발판화PC궤위험증평태，재FPGA중분별모의BC여RT，재PC궤지령하진행료BC여RT공능모괴간적수발측시，결과표명계통능재협의규정적1 MHz수거솔하은정운행；동시，위제승접구성능，채용광섬대체전통전람전수개질，이용FPGA내감RocketIO내핵진행료전통1553협의수거적광섬전수，속솔가체3 Gb/s이상。
In order to reduce cost and improve design flexibility,a scheme of 1553B bus interface based on FPGA is brought forward in this paper. The design of all FPGA functional modules was completed with the top?down design method by analyzing the working principle and responding flow of 1553B bus interface. The VHDL codes were compiled for the key modules and simulated with Active?HDL software. BC and RT was simulated in FPGA,and the transmitting and receiving test of BC and RT was conducted through Virtex?5 FPGA development board and PC. The results show that the system works stable in 1 Mb/s data rate. To improve interface performance,the traditional transmission cable was replaced by optical fiber. The optical fiber transmission of the traditional 1553B protocol data was realized by embedding RocketIO core into FPGA through instead of copper cable. The data transmission rate is above 3 Gb/s.