电子元件与材料
電子元件與材料
전자원건여재료
ELECTRONIC COMPONENTS & MATERIALS
2015年
2期
43-46
,共4页
功率器件%终端%VLD%掺杂曲线%耐压%可靠性
功率器件%終耑%VLD%摻雜麯線%耐壓%可靠性
공솔기건%종단%VLD%참잡곡선%내압%가고성
power device%termination%VLD%doping curve%breakdown voltage%reliability
采用横向变掺杂（Varied Lateral Doping, VLD）终端设计，通过推导菲克第二定律得到了线性变化的P阱掺杂曲线边端，并讨论了线性掺杂曲线与终端耐压之间的关系，最终在此基础上设计了一款900 V VDMOS功率器件。在140μm终端长度上仿真实现了947 V的耐压，且最大表面电场强度为1.65×105 V/cm，有效提高了终端的可靠性；与传统功率器件的制造工艺兼容，同时没有增加额外的掩膜与工艺步骤。
採用橫嚮變摻雜（Varied Lateral Doping, VLD）終耑設計，通過推導菲剋第二定律得到瞭線性變化的P阱摻雜麯線邊耑，併討論瞭線性摻雜麯線與終耑耐壓之間的關繫，最終在此基礎上設計瞭一款900 V VDMOS功率器件。在140μm終耑長度上倣真實現瞭947 V的耐壓，且最大錶麵電場彊度為1.65×105 V/cm，有效提高瞭終耑的可靠性；與傳統功率器件的製造工藝兼容，同時沒有增加額外的掩膜與工藝步驟。
채용횡향변참잡（Varied Lateral Doping, VLD）종단설계，통과추도비극제이정률득도료선성변화적P정참잡곡선변단，병토론료선성참잡곡선여종단내압지간적관계，최종재차기출상설계료일관900 V VDMOS공솔기건。재140μm종단장도상방진실현료947 V적내압，차최대표면전장강도위1.65×105 V/cm，유효제고료종단적가고성；여전통공솔기건적제조공예겸용，동시몰유증가액외적엄막여공예보취。
A varied lateral doping (VLD) method was adopted for terminal design of VDMOS. With the help of Fick’s second law, a linearly varied P well doping curve verge was achieved and applied in VLD design. The connection between linearly doping curve as well as breakdown voltage was discussed. The termination structure of 900 V VDMOS was made by VLD. By simulation, a breakdown-voltage of 947 V is achieved with 140 μm length termination structure, meanwhile, the device’s surface max electric-field intensity achieves 1.65×105 V/cm. The termination reliability is increased. The process technology is simple, without additional masks and steps.
