电子元件与材料
電子元件與材料
전자원건여재료
ELECTRONIC COMPONENTS & MATERIALS
2015年
2期
31-34
,共4页
邱美艳%赵晓宾%于冬安%张庆宝
邱美豔%趙曉賓%于鼕安%張慶寶
구미염%조효빈%우동안%장경보
非晶硅%叠层电池%本征层%沉积%短路电流%工艺参数
非晶硅%疊層電池%本徵層%沉積%短路電流%工藝參數
비정규%첩층전지%본정층%침적%단로전류%공예삼수
a-Si%tandem cell%intrinsic layer%deposition%short-circuit current%process parameters
采用PECVD技术制备a-Si:H/a-Si:H叠层双结非晶硅电池,研究了本征层厚度对叠层电池功率及短路电流的影响。通过调节顶电池和底电池本征层的沉积时间,得到不同厚度比例的本征层(di1:di2),经过实验对比发现 I层总体厚度为650 nm,di1:di2=1:5时得到的电池组件短路电流(Isc)和最大功率(Pmax)都是最大值。此时叠层电池的电流得到了较好的匹配,实现了工艺参数的优化。
採用PECVD技術製備a-Si:H/a-Si:H疊層雙結非晶硅電池,研究瞭本徵層厚度對疊層電池功率及短路電流的影響。通過調節頂電池和底電池本徵層的沉積時間,得到不同厚度比例的本徵層(di1:di2),經過實驗對比髮現 I層總體厚度為650 nm,di1:di2=1:5時得到的電池組件短路電流(Isc)和最大功率(Pmax)都是最大值。此時疊層電池的電流得到瞭較好的匹配,實現瞭工藝參數的優化。
채용PECVD기술제비a-Si:H/a-Si:H첩층쌍결비정규전지,연구료본정층후도대첩층전지공솔급단로전류적영향。통과조절정전지화저전지본정층적침적시간,득도불동후도비례적본정층(di1:di2),경과실험대비발현 I층총체후도위650 nm,di1:di2=1:5시득도적전지조건단로전류(Isc)화최대공솔(Pmax)도시최대치。차시첩층전지적전류득도료교호적필배,실현료공예삼수적우화。
PECVD technology was used to prepare a-Si:H/a-Si:H tandem cells. The effects of intrinsic layer thickness on short circuit current matching and power output of tandem cells were investigated. Different thickness ratios(di1:di2) of the intrinsic layer were gotten by changing the deposition time of the top cell and the bottom cell. Through experimental comparison, it is found that the short-circuit current (Isc) and the max Power (Pmax) are maximum when the intrinsic layer thickness is 650 nm and di1:di2 is 1:5. In this condition, the tandem cell has a better current matching, and the optimization of process parameters is achieved.