现代电子技术
現代電子技術
현대전자기술
MODERN ELECTRONICS TECHNIQUE
2015年
4期
125-128
,共4页
VMM%L2 Cache%功能验证%System Verilog%功能覆盖率%重用性
VMM%L2 Cache%功能驗證%System Verilog%功能覆蓋率%重用性
VMM%L2 Cache%공능험증%System Verilog%공능복개솔%중용성
VMM%L2 Cache%function verification%System Verilog%function coverage rate%reusability
随着集成电路行业的不断发展，芯片设计规模空前增长，功能也越来越复杂，使得验证的难度和重要性日益增大。在此提出一种由SystemVerilog语言搭建的基于VMM的一种面向对象的验证平台。该验证平台主要使用覆盖率驱动的验证技术，并结合可约束随机测试和记分板技术，对一款多核处理器芯片中的L2 Cache进行功能验证。最后对验证平台的可重用性进行研究。实验结果表明，验证平台具有良好的激励生成机制，能够对L2 Cache模块的功能进行全面的验证；同时，验证平台经过少量更改就可以在基于标准的AXI接口的SoC验证平台之间重用，极大地提高了验证效率，缩短了验证时间。
隨著集成電路行業的不斷髮展，芯片設計規模空前增長，功能也越來越複雜，使得驗證的難度和重要性日益增大。在此提齣一種由SystemVerilog語言搭建的基于VMM的一種麵嚮對象的驗證平檯。該驗證平檯主要使用覆蓋率驅動的驗證技術，併結閤可約束隨機測試和記分闆技術，對一款多覈處理器芯片中的L2 Cache進行功能驗證。最後對驗證平檯的可重用性進行研究。實驗結果錶明，驗證平檯具有良好的激勵生成機製，能夠對L2 Cache模塊的功能進行全麵的驗證；同時，驗證平檯經過少量更改就可以在基于標準的AXI接口的SoC驗證平檯之間重用，極大地提高瞭驗證效率，縮短瞭驗證時間。
수착집성전로행업적불단발전，심편설계규모공전증장，공능야월래월복잡，사득험증적난도화중요성일익증대。재차제출일충유SystemVerilog어언탑건적기우VMM적일충면향대상적험증평태。해험증평태주요사용복개솔구동적험증기술，병결합가약속수궤측시화기분판기술，대일관다핵처리기심편중적L2 Cache진행공능험증。최후대험증평태적가중용성진행연구。실험결과표명，험증평태구유량호적격려생성궤제，능구대L2 Cache모괴적공능진행전면적험증；동시，험증평태경과소량경개취가이재기우표준적AXI접구적SoC험증평태지간중용，겁대지제고료험증효솔，축단료험증시간。
With the continuous development of the integrated circuit industry,the scale and complexity of the chip is in?creased significantly,which make the difficulty and importance of verification increased day by day. A object?oriented verifica?tion platform based on verification methodology manual(VMM)and built by SystemVerilog language is proposed in this paper. The platform which is used to verify the function of L2Cache in a multi?core processor chip is driven by coverage rate and com?bined with constraint?randomize test and scoreboard technology. The reusability of the platform is research. The experimental re?sults show that the verification platform has a good stimulus generation mechanism,which can conduct a comprehensive verifica?tion of the L2 Cache. With a little change,the platform can be reused between SoC verification platforms based on standard AXI interface. It significantly enhanced the efficiency and save the time of chip functional verification.
