计算机与现代化
計算機與現代化
계산궤여현대화
COMPUTER AND MODERNIZATION
2015年
1期
96-101
,共6页
于中权%王一诚%吴大庆%陈习元%张晓亮%梁永青
于中權%王一誠%吳大慶%陳習元%張曉亮%樑永青
우중권%왕일성%오대경%진습원%장효량%량영청
UART%FPGA%System Generator
UART%FPGA%System Generator
UART%FPGA%System Generator
UART%FPGA%System Generator
基于System Generator 系统级建模工具在Matlab／Simulink环境下完成了UART通讯模块的建模，并生成位流文件下载到Spartan-3E开发板的FPGA芯片中，实现UART通讯数据发送和接收功能。实验结果表明，System Generator 系统级建模工具不仅消除了原先系统工程师与软硬件工程师之间的隔阂，而且简化了传统的FPGA开发流程。
基于System Generator 繫統級建模工具在Matlab／Simulink環境下完成瞭UART通訊模塊的建模，併生成位流文件下載到Spartan-3E開髮闆的FPGA芯片中，實現UART通訊數據髮送和接收功能。實驗結果錶明，System Generator 繫統級建模工具不僅消除瞭原先繫統工程師與軟硬件工程師之間的隔閡，而且簡化瞭傳統的FPGA開髮流程。
기우System Generator 계통급건모공구재Matlab／Simulink배경하완성료UART통신모괴적건모，병생성위류문건하재도Spartan-3E개발판적FPGA심편중，실현UART통신수거발송화접수공능。실험결과표명，System Generator 계통급건모공구불부소제료원선계통공정사여연경건공정사지간적격애，이차간화료전통적FPGA개발류정。
The paper introduces the use of System Generator of Xilinx that is system level modeling tool in the MATLAB /Simulink environment for the completion of algorithm modeling of the UART procedure , generates the corresponding code to the FPGA , and realizes the function between UART communication data sending and receiving .Experiment results show that the System Genera-tor as a system level modeling tool is not only to eliminate the gap between the original system engineers and hardware and soft -ware engineers , but also to simplify the traditional development process of the FPGA .
