组合机床与自动化加工技术
組閤機床與自動化加工技術
조합궤상여자동화가공기술
MODULAR MACHINE TOOL & AUTOMATIC MANUFACTURING TECHNIQUE
2015年
1期
42-45
,共4页
于世华%闫庆鑫%齐献伟%袭萌萌%郑佳硕%王开宇
于世華%閆慶鑫%齊獻偉%襲萌萌%鄭佳碩%王開宇
우세화%염경흠%제헌위%습맹맹%정가석%왕개우
知识库%现场可编程门阵列%模糊PID%知识产权核
知識庫%現場可編程門陣列%模糊PID%知識產權覈
지식고%현장가편정문진렬%모호PID%지식산권핵
knowledge base%FPGA%fuzzy PID%IP core
优化知识库是提高模糊控制性能的关键和难点,文章结合传统模糊PID控制规则与理论知识,重点优化了比例系数和积分系数的推理规则,并在Matlab/Simulink仿真平台进行验证。优化后的控制器具有更强的适应性和鲁棒性,对于典型二阶系统,在阶跃输入条件下,上升时间与峰值时间均减少8ms,超调量下降2.18%,进入±5%误差带调整时间减少105ms,在高频扰动或被控参数变化频繁的场合尤其重要。同时,为使该控制器灵活运用于SOPC系统级设计,文章运用Verilog HDL描述语言,采用模块化设计方法,模糊推理部分采用离线计算、在线查表的方式,PID算法采用改进的增量式并行结构,实现了基于FPGA的模糊自适应PID控制器IP软核,简化了系统设计,降低了FPGA资源耗费。测试结果表明,该控制器IP软核结果正确有效,可以灵活调用。
優化知識庫是提高模糊控製性能的關鍵和難點,文章結閤傳統模糊PID控製規則與理論知識,重點優化瞭比例繫數和積分繫數的推理規則,併在Matlab/Simulink倣真平檯進行驗證。優化後的控製器具有更彊的適應性和魯棒性,對于典型二階繫統,在階躍輸入條件下,上升時間與峰值時間均減少8ms,超調量下降2.18%,進入±5%誤差帶調整時間減少105ms,在高頻擾動或被控參數變化頻繁的場閤尤其重要。同時,為使該控製器靈活運用于SOPC繫統級設計,文章運用Verilog HDL描述語言,採用模塊化設計方法,模糊推理部分採用離線計算、在線查錶的方式,PID算法採用改進的增量式併行結構,實現瞭基于FPGA的模糊自適應PID控製器IP軟覈,簡化瞭繫統設計,降低瞭FPGA資源耗費。測試結果錶明,該控製器IP軟覈結果正確有效,可以靈活調用。
우화지식고시제고모호공제성능적관건화난점,문장결합전통모호PID공제규칙여이론지식,중점우화료비례계수화적분계수적추리규칙,병재Matlab/Simulink방진평태진행험증。우화후적공제기구유경강적괄응성화로봉성,대우전형이계계통,재계약수입조건하,상승시간여봉치시간균감소8ms,초조량하강2.18%,진입±5%오차대조정시간감소105ms,재고빈우동혹피공삼수변화빈번적장합우기중요。동시,위사해공제기령활운용우SOPC계통급설계,문장운용Verilog HDL묘술어언,채용모괴화설계방법,모호추리부분채용리선계산、재선사표적방식,PID산법채용개진적증량식병행결구,실현료기우FPGA적모호자괄응PID공제기IP연핵,간화료계통설계,강저료FPGA자원모비。측시결과표명,해공제기IP연핵결과정학유효,가이령활조용。
Optimization of Knowledge Base is key and difficulty to improve the performance of fuzzy control. This paper adjusts and optimizes the inference rules of proportionality and integral coefficient of fuzzy PID controller by combining the theory analysis with conventional inference rules. Then it was tested on the simu-lation platform of MATLAB/SIMULINK. And it proves that the optimized controller has better robustness and adaptability than the previous one. For a typical second order system with a step input, the rise time and peak time was both reduced by 8ms, the overshoot by 2. 18% and the setting time( ± 5% ) by 105ms which is vital in the occasions containing high frequency disturbance and frequent changes of the parameters. Meanwhile, the Fuzzy self-turning PID IP (Intellectual Property) Core based on FPGA(Field Programmable Gate Array) was implemented by using Verilog HDL and modular design method, to make it be flexibly used in system de-sign based on SOPC (System on Programmable Chip). In this core designing, the modified incremental PID algorithm was used, and the part of fuzzy self-turning was replaced by on-line look-up table structure and off-line inference, thus simplifying this design and reducing the hardware resources. The simulation results shows that the IP core can achieve correct and effective results and can be flexibly called.