CAJ | 학술논문

文中介绍了符合CoreConnect规范的高性能处理器局部总线在SoC芯片中的应用。为了提高基于PPC架构的SoC芯片性能，增加存储带宽利用率，提出一种基于PLB双总线的高速存储接口的设计。文中还描述了高速从接口和DDR3控制器的体系架构设计，并通过对DDR3控制器的数据训练和自测试等关键技术和难点的介绍，实现了高速存储系统的设计。通过仿真可知，基于该接口的SoC芯片中DDR3 SDRAM的带宽利用率能提高到85%以上。通过PCB板上信号完整性分析表明，该接口应用于电路板上的走线串扰小，测试得到的眼图清晰端正，满足设计要求。
문중개소료부합CoreConnect규범적고성능처리기국부총선재SoC심편중적응용。위료제고기우PPC가구적SoC심편성능，증가존저대관이용솔，제출일충기우PLB쌍총선적고속존저접구적설계。문중환묘술료고속종접구화DDR3공제기적체계가구설계，병통과대DDR3공제기적수거훈련화자측시등관건기술화난점적개소，실현료고속존저계통적설계。통과방진가지，기우해접구적SoC심편중DDR3 SDRAM적대관이용솔능제고도85%이상。통과PCB판상신호완정성분석표명，해접구응용우전로판상적주선천우소，측시득도적안도청석단정，만족설계요구。
It introduces the application of PLB bus in the SoC,which follows CoreConnect bus specification. In order to improve the per-formance of SoC based on PowerPC and increase the storage bandwidth utilization,present an efficient memory interface based on two PLB,also introduce the architecture of high speed slave interface and of DDR3 controller. Through introducing the key techniques and dif-ficult problems of data training and self-test for DDR3 controller,implement the design of high speed memory system. According to sim-ulation result,the bandwidth utilization ratio of this memory interface can reach to 85%. The signal integrity analysis on PCB has presen-ted that the placement and routing is good and the read data-eye is complete and clear.