CAJ | 학술논문

以时序电路的可测性设计方法为主要研究内容，针对时序电路中由于时序元件的可观测性和可控制性比较差，导致测试生成难度较大，并且存在影响测试故障覆盖率的问题。以固定型故障模型的检测为研究基础，通过对时序电路进行扫描测试技术的可测性设计，解决时序电路中内部节点难以测试的问题。设计实现的目标是以尽可能少地插入可测性设计的硬件逻辑，提高被测时序电路的故障覆盖率。
이시서전로적가측성설계방법위주요연구내용，침대시서전로중유우시서원건적가관측성화가공제성비교차，도치측시생성난도교대，병차존재영향측시고장복개솔적문제。이고정형고장모형적검측위연구기출，통과대시서전로진행소묘측시기술적가측성설계，해결시서전로중내부절점난이측시적문제。설계실현적목표시이진가능소지삽입가측성설계적경건라집，제고피측시서전로적고장복개솔。
Because of temporal element in sequential circuits with poor observability and controllability ,the test generation leads to be difficult ,and the fault coverage problems will occur .The design of sequential circuits is studied .Base on a fixed type failure model ,through the study of the scanning measurement technology of sequential circuits of measurability design ,the problem of internal nodes in the sequential circuits is difficult to test .This design will realize the as little as possible goals on insertion measurability design of the hardware logic ,and improve the fault coverage of the sequential circuit under test .