电子设计工程
電子設計工程
전자설계공정
ELECTRONIC DESIGN ENGINEERING
2015年
8期
154-157,161
,共5页
唐坤%葛华勇%房树娟
唐坤%葛華勇%房樹娟
당곤%갈화용%방수연
YASS算法%图像隐写%隐写分析%虚拟嵌入块%信道选择%最小嵌入失真
YASS算法%圖像隱寫%隱寫分析%虛擬嵌入塊%信道選擇%最小嵌入失真
YASS산법%도상은사%은사분석%허의감입괴%신도선택%최소감입실진
YASS algorithm%image steganography%steganalysis%virtual host block%channel choice%MED
为抵抗YASS隐写分析算法,本文提出一种新的YASS改进算法。该算法首先利用密钥选择不规则的区域,生成一个虚拟的8×8嵌入块;然后根据图像自身特点,提出一种最小化嵌入失真的计算方法,对嵌入块修改后的量化DCT系数进行失真分析,选择失真影响最小的交流DCT系数进行秘密信息嵌入,取代传统方法直观选择前19交流DCT系数。将文中改进算法与虚拟嵌入块YASS(VH-YASS)算法进行了对比实验,实验结果证明,依据嵌入失真由小到大的顺序选择嵌入信道,在抵抗隐写分析和视觉质量方面都优于VH-YASS隐写方法。
為牴抗YASS隱寫分析算法,本文提齣一種新的YASS改進算法。該算法首先利用密鑰選擇不規則的區域,生成一箇虛擬的8×8嵌入塊;然後根據圖像自身特點,提齣一種最小化嵌入失真的計算方法,對嵌入塊脩改後的量化DCT繫數進行失真分析,選擇失真影響最小的交流DCT繫數進行祕密信息嵌入,取代傳統方法直觀選擇前19交流DCT繫數。將文中改進算法與虛擬嵌入塊YASS(VH-YASS)算法進行瞭對比實驗,實驗結果證明,依據嵌入失真由小到大的順序選擇嵌入信道,在牴抗隱寫分析和視覺質量方麵都優于VH-YASS隱寫方法。
위저항YASS은사분석산법,본문제출일충신적YASS개진산법。해산법수선이용밀약선택불규칙적구역,생성일개허의적8×8감입괴;연후근거도상자신특점,제출일충최소화감입실진적계산방법,대감입괴수개후적양화DCT계수진행실진분석,선택실진영향최소적교류DCT계수진행비밀신식감입,취대전통방법직관선택전19교류DCT계수。장문중개진산법여허의감입괴YASS(VH-YASS)산법진행료대비실험,실험결과증명,의거감입실진유소도대적순서선택감입신도,재저항은사분석화시각질량방면도우우VH-YASS은사방법。
This paper proposed a new YASS algorithm to resist steganalysis. Virtual embedding blocks are generated firstly by using a key to select random region. Then a calculation method for minimizing embedding distortion is put forward and the quantized DCT coefficients for embedding the modified block distortion is analyzed. Secret information is embedded by selecting AC DCT coefficients which have the minimum distortion effects, instead of traditional algorithm which selects the first 19 AC DCT coefficients instinctively. The proposed algorithm is compared with VH-YASS algorithm by experiments.The experimental results show that the embedded channel choice based on embedding distortion ascending order is better than VH-YASS steganography methods in terms of resistance steganalysis and visual quality.