CAJ | 학술논문

为了提升密码算法中抽取、移位等位操作的处理效率，降低抽取和移位实现的硬件资源消耗，构建了以iB‐utterfly网络为基础的高速可重构抽取移位硬件架构，提出架构所需的路由信息生成算法并进行高速硬件映射。最后对架构进行性能评估，结果表明，提出的抽取移位单元具有较高的处理效率和灵活性，在CMOS 65 nm 工艺下，32比特抽取移位工作频率可达到2 G Hz 。
위료제승밀마산법중추취、이위등위조작적처리효솔，강저추취화이위실현적경건자원소모，구건료이iB‐utterfly망락위기출적고속가중구추취이위경건가구，제출가구소수적로유신식생성산법병진행고속경건영사。최후대가구진행성능평고，결과표명，제출적추취이위단원구유교고적처리효솔화령활성，재CMOS 65 nm 공예하，32비특추취이위공작빈솔가체도2 G Hz 。
In order to enhance processing efficiency and reduce hardware resource consumption of the extraction replacement and shift replacement in cipher algorithm , a high‐speed reconfigurable extraction‐shift hardware architecture based on iButterfly is constructed in this paper .At the same time ,the generating routing information of framework are put forward , then mapping high‐speed hardware is realized . Finally , the results show that the proposed extraction‐shift units have high efficiency and flexibility .The number of 32‐bit extraction‐shift replacement operating frequency is 2 GHz under the CMOS 65 nm .