微电子学与计算机
微電子學與計算機
미전자학여계산궤
MICROELECTRONICS & COMPUTER
2015年
4期
75-78
,共4页
2D-M esh%NoC%电路交换%XY路由算法
2D-M esh%NoC%電路交換%XY路由算法
2D-M esh%NoC%전로교환%XY로유산법
2D-Mesh%NoC%circuit switching%XY routing algorithm
针对传统总线系统架构的缺点，为提高多核系统性能，设计了一个2D‐Mesh Network‐on‐chip（NoC）片上网络，通过片上网络中的路由器来连接芯片上的各个处理器核，实现核间通信．2D‐M esh拓扑结构、电路交换技术和XY路由算法保证了系统的延迟和吞吐量，硬件设计语言Verilog HDL物理实现NoC ．利用Altera公司的FP‐GA开发板对本文设计的片上网络NoC进行测试，测试结果表明本文所设计的片上网络是正确的，能有效的完成系统通信．
針對傳統總線繫統架構的缺點，為提高多覈繫統性能，設計瞭一箇2D‐Mesh Network‐on‐chip（NoC）片上網絡，通過片上網絡中的路由器來連接芯片上的各箇處理器覈，實現覈間通信．2D‐M esh拓撲結構、電路交換技術和XY路由算法保證瞭繫統的延遲和吞吐量，硬件設計語言Verilog HDL物理實現NoC ．利用Altera公司的FP‐GA開髮闆對本文設計的片上網絡NoC進行測試，測試結果錶明本文所設計的片上網絡是正確的，能有效的完成繫統通信．
침대전통총선계통가구적결점，위제고다핵계통성능，설계료일개2D‐Mesh Network‐on‐chip（NoC）편상망락，통과편상망락중적로유기래련접심편상적각개처리기핵，실현핵간통신．2D‐M esh탁복결구、전로교환기술화XY로유산법보증료계통적연지화탄토량，경건설계어언Verilog HDL물리실현NoC ．이용Altera공사적FP‐GA개발판대본문설계적편상망락NoC진행측시，측시결과표명본문소설계적편상망락시정학적，능유효적완성계통통신．
Considering the shortcomings of the traditional bus system architecture ,in order to improve the multi‐core system performance ,Mesh Network‐on‐chip (NoC) is designed in this paper .Processor core on the chip links each other through the routers in the NoC ,and the communication between nuclears are implemented .The 2D‐Mesh topology structure ,circuit switching technology and XY routing algorithm can guarantee the delay and throughput of the system ,and hardware design language Verilog HDL achieved physical NoC .The FPGA Development Board of Altera company was used to test the NoC ,the test result shows that this design on the NoC is correct ,and can complete system communication effectively .
