微电子学与计算机
微電子學與計算機
미전자학여계산궤
MICROELECTRONICS & COMPUTER
2015年
4期
65-69
,共5页
李聪%任志雄%万美琳%韩爽%戴葵
李聰%任誌雄%萬美琳%韓爽%戴葵
리총%임지웅%만미림%한상%대규
功率放大器%射频%三阶交调失真%线性度提高%电容补偿%低功耗
功率放大器%射頻%三階交調失真%線性度提高%電容補償%低功耗
공솔방대기%사빈%삼계교조실진%선성도제고%전용보상%저공모
power amplifier%radio frequency%the third-order intermodulation distortion%linearity enhancement%capacitance compensation%lower power
设计了一种带电容补偿的2.45 GHz高线性度、低功耗CMOS功率放大器(PA).电路设计采用了差分结构,工作在AB类放大状态下.驱动级采用共源共栅结构,为下一级提供大的电压输出摆幅,功放级采用共源结构,负载采用LC谐振网络,提供大的输出功率.此外,设计从M OS管级对PA进行了优化,提出了PM OS管电容补偿技术,通过补偿栅源电容(Cgs ),使得三阶交调失真(IMD3)减小了10 dBc ,从而提高了 PA 的线性度,并实现低功耗.电路采用TSMC 0.18μm RF CMOS工艺设计仿真,结果表明:在2.45GHz工作点处,PA的输入反射系数小于-20 dB ,功率增益为25 dB ,功率附加效率(PAE)为27%,三阶交调失真小于-42 dBc .
設計瞭一種帶電容補償的2.45 GHz高線性度、低功耗CMOS功率放大器(PA).電路設計採用瞭差分結構,工作在AB類放大狀態下.驅動級採用共源共柵結構,為下一級提供大的電壓輸齣襬幅,功放級採用共源結構,負載採用LC諧振網絡,提供大的輸齣功率.此外,設計從M OS管級對PA進行瞭優化,提齣瞭PM OS管電容補償技術,通過補償柵源電容(Cgs ),使得三階交調失真(IMD3)減小瞭10 dBc ,從而提高瞭 PA 的線性度,併實現低功耗.電路採用TSMC 0.18μm RF CMOS工藝設計倣真,結果錶明:在2.45GHz工作點處,PA的輸入反射繫數小于-20 dB ,功率增益為25 dB ,功率附加效率(PAE)為27%,三階交調失真小于-42 dBc .
설계료일충대전용보상적2.45 GHz고선성도、저공모CMOS공솔방대기(PA).전로설계채용료차분결구,공작재AB류방대상태하.구동급채용공원공책결구,위하일급제공대적전압수출파폭,공방급채용공원결구,부재채용LC해진망락,제공대적수출공솔.차외,설계종M OS관급대PA진행료우화,제출료PM OS관전용보상기술,통과보상책원전용(Cgs ),사득삼계교조실진(IMD3)감소료10 dBc ,종이제고료 PA 적선성도,병실현저공모.전로채용TSMC 0.18μm RF CMOS공예설계방진,결과표명:재2.45GHz공작점처,PA적수입반사계수소우-20 dB ,공솔증익위25 dB ,공솔부가효솔(PAE)위27%,삼계교조실진소우-42 dBc .
A 2 .45 GHz high linearity and low power CMOS power amplifier (PA) with capacitance compensation is designed in this paper ,which uses differential constructor and works in class of AB .The driver stage uses common source common gate architecture to provide large output voltage swing for the next stage ,and the power stage uses common gate architecture with LC resonance as load impedance to provide large output power .Besides ,the PA is optimized from MOSFETs ,and PMOS capacitance compensation is raised to enhance linearity and realize low power through compensating the gate‐source capacitance (Cgs ) and decreasing the third‐order inter‐modulation distortion (IMD3) by 10 dBc .The proposed PA is designed and simulated on the basis of TSMC 0 .18μm RF CMOS process . Simulation results show that the PA's reflection coefficient is less than ‐20 dB ,power gain is 25dB ,power‐added efficiency(PAE) is 27% ,and the third‐order inter‐modulation distortion (IMD3) is less than‐42dBc at 2 .45 GHz .