CAJ | 학술논문

首先设计了一种基于MDLL的数控振荡器（DCO），进而实现了一种基于DCO的全数字可配置的数字频率合成器（DFS），输出时钟频率等于参考时钟频率乘以 M除以D ，实现了类似于MDLL的抖动特性．频率合成器提供一个可配置的倍频因子 M和一个分频因子D ，其范围为2～32和1～32，用户可以通过对 M和D的配置，实现任意倍数的频率合成．所设计的DFS采用 TSMC的0．13 mm标准CMOS工艺实现，版图面积为480μm ×120μm ．DFS的输出频率范围为15～400 M Hz ，输入频率范围为1～270 M Hz ．输出频率为270 M Hz时实测的相位噪声为－110．01 dBc／Hz＠1 M Hz ．
수선설계료일충기우MDLL적수공진탕기（DCO），진이실현료일충기우DCO적전수자가배치적수자빈솔합성기（DFS），수출시종빈솔등우삼고시종빈솔승이 M제이D ，실현료유사우MDLL적두동특성．빈솔합성기제공일개가배치적배빈인자 M화일개분빈인자D ，기범위위2～32화1～32，용호가이통과대 M화D적배치，실현임의배수적빈솔합성．소설계적DFS채용 TSMC적0．13 mm표준CMOS공예실현，판도면적위480μm ×120μm ．DFS적수출빈솔범위위15～400 M Hz ，수입빈솔범위위1～270 M Hz ．수출빈솔위270 M Hz시실측적상위조성위－110．01 dBc／Hz＠1 M Hz ．
This paper presents a digitally controlled oscillator (DCO ) based on a multiplying delay locked loop (MDLL) ,and a DCO‐based configurable digital frequency synthesizer (DFS) is implemented .The output clock frequency is equal to the reference clock frequency multiplied by M divided by D .The multiplication ratio M and division ratio D can be programmed from 2 to 32 ,and 1 to 32 ,respectively .The frequency synthesizer achieves similar jitter performance as conventional MDLL .The DFS is implemented in TSMC 0 .13‐μm CMOS technology , with a layout area of 480 μm × 120 μm .The frequency range of the input and output clock are 1 ~ 270 M Hz and 15~ 400 MHz ,respectively .The measured phase noise is‐110 .01 dBc/Hz@ 1 MHz ,when the output clock frequency is 270 M Hz .