CAJ | 학술논문

提出一种基于S3C6410A的抗干扰数据电能校验调度嵌入式系统的设计，通过抗干扰数据的检测，对检测参数进行数据电能校验调度，建立一个基于S3C6410A抗干扰核心处理器与嵌入式操作系统的设计平台，利用高效能的方法检测干扰数据，通过对抗干扰数据的分析，并进行电能校验调度，建立嵌入式系统设计程序，完成对其数据参数进行分析的过程。仿真实验表明，基于S3C6410A的抗干扰数据电能校验调度嵌入式系统能够通过定义抗干扰数据模型来实现对旧方法的改变，且可灵活增加或删除相应验证的能力，满足嵌入式系统设计模型重复验证和评估的要求，从而得到更为高性能、低功耗、低成本的抗干扰数据电能校验调度嵌入式系统，促进了嵌入式系统设计方法的新发展。
제출일충기우S3C6410A적항간우수거전능교험조도감입식계통적설계，통과항간우수거적검측，대검측삼수진행수거전능교험조도，건립일개기우S3C6410A항간우핵심처리기여감입식조작계통적설계평태，이용고효능적방법검측간우수거，통과대항간우수거적분석，병진행전능교험조도，건립감입식계통설계정서，완성대기수거삼수진행분석적과정。방진실험표명，기우S3C6410A적항간우수거전능교험조도감입식계통능구통과정의항간우수거모형래실현대구방법적개변，차가령활증가혹산제상응험증적능력，만족감입식계통설계모형중복험증화평고적요구，종이득도경위고성능、저공모、저성본적항간우수거전능교험조도감입식계통，촉진료감입식계통설계방법적신발전。
The embedded system design system with limited resources and high reliability requirements for the operating system and processor weak anti-interference ability. For this, put forward a kind of anti-interference power calibration data scheduling based on S3C6410A embedded system design, through the establishment of a core processor and embedded op?erating system based on S3C6410A anti-interference of embedded development module, the interference data were listen?ing to intercept the process of data analysis. Simulation experiments show that the anti-interference power calibration data scheduling based on S3C6410A embedded system can be implemented by defining the anti-interference data model to the change of the old method, and the flexible ability to add or delete the corresponding verification, validation and repeatedly embedded system design model assessment requirements, so as to get more.