组合机床与自动化加工技术
組閤機床與自動化加工技術
조합궤상여자동화가공기술
MODULAR MACHINE TOOL & AUTOMATIC MANUFACTURING TECHNIQUE
2015年
4期
19-23,28
,共6页
岑誉%高健%曾友%简川霞
岑譽%高健%曾友%簡川霞
잠예%고건%증우%간천하
PCB%圆形基准点%亚像素%边缘提取%加权椭圆拟合
PCB%圓形基準點%亞像素%邊緣提取%加權橢圓擬閤
PCB%원형기준점%아상소%변연제취%가권타원의합
PCB%circular mark%sub pixel%edge extraction%weighted ellipse fitting
针对贴片机视觉系统对印刷电路板( PCB)圆形基准点快速精密定位的要求,提出基于形态学的基准点区域提取方法,对约化后的基准点进行像素级边缘提取,进而采用一维曲线拟合法提取出亚像素级边缘;在此基础上,提出一种圆形基准点边缘轮廓的权重式椭圆拟合定位算法,减少边缘轮廓点大离群值对拟合精度的影响,获到高精度的基准点中心位置。该算法通过设置椭圆约束条件,可避免零解和成比例解的出现,提高计算的速度和精度。仿真实验结果表明,所提的方法耗时25 ms左右,基准点中心的位置误差小于0.03pixel,相比于其它定位方法,该方法在耗时和定位精度方面具有明显优势。在实验室搭建的视觉检测平台上开展进一步的实验验证,对实际采集到的PCB基准点图像可实现快速精确的基准点中心坐标提取,基准点拟合椭圆的形状误差均值为0.1pixel,能满足贴片机视觉系统快速精密的定位要求。
針對貼片機視覺繫統對印刷電路闆( PCB)圓形基準點快速精密定位的要求,提齣基于形態學的基準點區域提取方法,對約化後的基準點進行像素級邊緣提取,進而採用一維麯線擬閤法提取齣亞像素級邊緣;在此基礎上,提齣一種圓形基準點邊緣輪廓的權重式橢圓擬閤定位算法,減少邊緣輪廓點大離群值對擬閤精度的影響,穫到高精度的基準點中心位置。該算法通過設置橢圓約束條件,可避免零解和成比例解的齣現,提高計算的速度和精度。倣真實驗結果錶明,所提的方法耗時25 ms左右,基準點中心的位置誤差小于0.03pixel,相比于其它定位方法,該方法在耗時和定位精度方麵具有明顯優勢。在實驗室搭建的視覺檢測平檯上開展進一步的實驗驗證,對實際採集到的PCB基準點圖像可實現快速精確的基準點中心坐標提取,基準點擬閤橢圓的形狀誤差均值為0.1pixel,能滿足貼片機視覺繫統快速精密的定位要求。
침대첩편궤시각계통대인쇄전로판( PCB)원형기준점쾌속정밀정위적요구,제출기우형태학적기준점구역제취방법,대약화후적기준점진행상소급변연제취,진이채용일유곡선의합법제취출아상소급변연;재차기출상,제출일충원형기준점변연륜곽적권중식타원의합정위산법,감소변연륜곽점대리군치대의합정도적영향,획도고정도적기준점중심위치。해산법통과설치타원약속조건,가피면영해화성비예해적출현,제고계산적속도화정도。방진실험결과표명,소제적방법모시25 ms좌우,기준점중심적위치오차소우0.03pixel,상비우기타정위방법,해방법재모시화정위정도방면구유명현우세。재실험실탑건적시각검측평태상개전진일보적실험험증,대실제채집도적PCB기준점도상가실현쾌속정학적기준점중심좌표제취,기준점의합타원적형상오차균치위0.1pixel,능만족첩편궤시각계통쾌속정밀적정위요구。
In order to meet the chip mounter vision system requirement for the fast and precise location of circular mark on printed circuit board( PCB) , a mark region extraction method based on the morphology was proposed. After that, the pixel edge was extracted from the simplified mark image and then the sub-pixel edge was extracted by one-dimensional curve fitting. On this basis,a location algorithm based on weighted el-lipse fitting for circular mark edge contour was proposed to reduce the impact of large outliers of edge con-tour points and acquire high-precision mark centre position. The algorithm could avoid the zero and propor-tionable solutions and improve the computational speed and accuracy by setting elliptical constraint. The sim-ulation experiment result indicates that with the proposed method, the elapsed time is about 25ms, the posi-tion error of mark centre is less than 0. 03pixel. The method has a significant advantage in elapsed time and precision over the other location methods. The further experiment testing on visual inspection platform indi-cates that the mark centre can be located fast and precisely from the real PCB mark image and the mean form errors of fitted ellipse are just 0. 1pixel, which meets the chip mounter visual system requirement for speedi-ness and high precision.