新技术新工艺
新技術新工藝
신기술신공예
NEW TECHNOLOGY & NEW PROCESS
2015年
4期
40-42
,共3页
张泽%刘慧慧%田涛%梁天泰%周英杰
張澤%劉慧慧%田濤%樑天泰%週英傑
장택%류혜혜%전도%량천태%주영걸
Verilog HDL%FPGA%计数%分频%仿真%占空比
Verilog HDL%FPGA%計數%分頻%倣真%佔空比
Verilog HDL%FPGA%계수%분빈%방진%점공비
Verilog HDL%FPGA%count%frequency divider%simulation%duty cycle
简单介绍了主要的时钟分频方法,提出了FPGA内部PLL分频的局限性,给出了基于 Ver-ilog HDL的整数分频方法。编写了Verilog HDL程序,实现了基于 FPGA 硬件平台的占空比为50%的任意整数分频。结合 Quartus开发平台和Modelsim仿真软件验证表明,该分频方法简单、实用。采用该方法,替换N值可实现任意整数等占空比的分频。
簡單介紹瞭主要的時鐘分頻方法,提齣瞭FPGA內部PLL分頻的跼限性,給齣瞭基于 Ver-ilog HDL的整數分頻方法。編寫瞭Verilog HDL程序,實現瞭基于 FPGA 硬件平檯的佔空比為50%的任意整數分頻。結閤 Quartus開髮平檯和Modelsim倣真軟件驗證錶明,該分頻方法簡單、實用。採用該方法,替換N值可實現任意整數等佔空比的分頻。
간단개소료주요적시종분빈방법,제출료FPGA내부PLL분빈적국한성,급출료기우 Ver-ilog HDL적정수분빈방법。편사료Verilog HDL정서,실현료기우 FPGA 경건평태적점공비위50%적임의정수분빈。결합 Quartus개발평태화Modelsim방진연건험증표명,해분빈방법간단、실용。채용해방법,체환N치가실현임의정수등점공비적분빈。
A brief introduction for the main clock division method was given,put forward limitations of FPGA internal PLL frequency divider,and gave the integer divide method based on Verilog HDL.Wrote Verilog HDL program,realized an arbitrary integer divider that the duty cycle is 50% and based on the hardware platform of the FPGA.Combined with Quartus development platform and Modelsim simulation software validation,the results showed that the frequency division method is simple and practical.By using this method,the replacement value of N can realize any integer frequency divider that duty cycle.