CAJ | 학술논문

目的：研究采样频率为2~10 MHz的64通道超高速同步瞬态测试系统的设计技术，实现两类典型超高速瞬态测试系统的硬件架构设计与软件架构设计。方法一类采用PXI-Express高带宽总线和高速RAID磁盘阵列架构构建持续流盘存储的连续高速测试系统，另一类是采用大容量板载数据缓存和PXI总线事后下载传输数据的架构构造高速测试系统。在高性能测试软件设计方面，主要应用生产者/消费者结构与有限状态机相结合的软件架构进行高性能测试系统软件设计。结果目前64通道下基于持续流盘架构的测试系统受数据记录的速度限制系统最高采样频率仅达2.5 MHz，而基于板载缓存数据与PXI总线事后下载数据架构的测试系统最高采样频率可达10 MHz，测试时长可达5s。结论当前两类架构的测试系统均可满足超高速瞬态测试需求，设计时需根据需求的最高采样频率决定使用的架构形式。
목적：연구채양빈솔위2~10 MHz적64통도초고속동보순태측시계통적설계기술，실현량류전형초고속순태측시계통적경건가구설계여연건가구설계。방법일류채용PXI-Express고대관총선화고속RAID자반진렬가구구건지속류반존저적련속고속측시계통，령일류시채용대용량판재수거완존화PXI총선사후하재전수수거적가구구조고속측시계통。재고성능측시연건설계방면，주요응용생산자/소비자결구여유한상태궤상결합적연건가구진행고성능측시계통연건설계。결과목전64통도하기우지속류반가구적측시계통수수거기록적속도한제계통최고채양빈솔부체2.5 MHz，이기우판재완존수거여PXI총선사후하재수거가구적측시계통최고채양빈솔가체10 MHz，측시시장가체5s。결론당전량류가구적측시계통균가만족초고속순태측시수구，설계시수근거수구적최고채양빈솔결정사용적가구형식。
Objective The design technique for 64 channels ultrahigh-speed synchronous transient testing system with data sampling frequency of 2 MHz-10 MHz was researched, in order to realize the design of hardware architecture and software architecture for two kinds of typical ultrahigh-speed transient testing systems. Methods For hardware architecture, the continuous high-speed test system with continuous flow disk storage constructed based on PXI-Express bus data transmission and RAID array stream disk data saving and the high-speed test system constructed based on large capacity on-board cache data saving and bus downloading transmission were applied in detail. For high-performance system software design, the design technique with application of producer/consumer architecture and finite state machine was applied. Results Currently, for system with 64 channels, the data sampling frequency could only reach 2.5 MHz with the limitation of file writing speed based on PXI Express bus and raid array stream disk data saving architecture, while the data sampling frequency could reach 10 MHz based on architecture with on-board cache data and PXI bus downloading data, in this condition, the test time of the system could reach 5 s. Conclusion These two kinds of test systems could both meet the requirements of ultrahigh-speed transient test, and the system architecture could be decided by the maximum sampling frequency required.